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igt@kms_pipe_crc_basic@* - incomplete - no useful logs
Stdout
Starting dynamic subtest: pipe-B-DP-3
[cmd] rtcwake: wakeup from "mem" using /dev/rtc0 at Wed Aug 9 13:54:47 2023
Stderr
Starting dynamic subtest: pipe-B-DP-3
Dmesg
<6> [994.692435] [IGT] kms_pipe_crc_basic: starting dynamic subtest pipe-B-DP-3
<7> [994.694255] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 0, size: 8388608
<7> [994.694637] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 1, size: 8388608
<7> [994.694853] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 2, size: 8388608
<7> [994.695056] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 3, size: 4194304
<7> [994.695260] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 4, size: 2097152
<7> [994.695467] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 5, size: 1048576
<7> [994.695664] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 6, size: 524288
<7> [994.695861] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 7, size: 131072
<7> [994.696060] xe 0000:03:00.0: [drm:xe_migrate_clear [xe]] Pass 8, size: 65536
<7> [994.696356] xe 0000:03:00.0: [drm:drm_mode_addfb2 [drm]] [FB:290]
<7> [994.704471] xe 0000:03:00.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [994.704595] xe 0000:03:00.0: [drm:gen9_enable_dc5 [xe]] Enabling DC5
<7> [994.704714] xe 0000:03:00.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 01
<7> [994.705094] xe 0000:03:00.0: [drm:intel_power_well_disable [xe]] disabling always-on
<7> [994.717073] xe 0000:03:00.0: [drm:intel_power_well_enable [xe]] enabling always-on
<7> [994.717181] xe 0000:03:00.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [994.717406] xe 0000:03:00.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 01 to 00
<7> [994.719207] [drm:drm_mode_setcrtc [drm]] [CRTC:80:pipe A]
<7> [994.727314] [drm:drm_mode_setcrtc [drm]] [CRTC:131:pipe B]
<7> [994.727406] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:264:DP-3]
<7> [994.727815] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:264:DP-3] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [994.727934] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link computation with max lane count 4 max rate 810000 max bpp 30 pixel clock 537600KHz
<7> [994.728040] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp 30
<7> [994.728146] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link rate required 2016000 available 2160000
<7> [994.728251] xe 0000:03:00.0: [drm:intel_dp_compute_config [xe]] [CONNECTOR:264:DP-3] SDP split enable: no
<7> [994.728360] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:131:pipe B] hw max bpp: 30, pipe bpp: 30, dithering: 0
<7> [994.728475] xe 0000:03:00.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:263:DDI C/PHY C] [CRTC:131:pipe B]
<7> [994.728582] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.enable (expected 0, found 1)
<7> [994.728688] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.active (expected 0, found 1)
<7> [994.728795] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in cpu_transcoder (expected -1, found 1)
<7> [994.728900] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in lane_count (expected 0, found 4)
<7> [994.729005] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in dp_m_n (expected tu 0 data 0/0 link 0/0, found tu 64, data 7829367/8388608 link 521957/524288)
<7> [994.729111] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in output_types (expected 0x00000000, found 0x00000080)
<7> [994.729217] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in framestart_delay (expected 0, found 1)
<7> [994.729323] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_hdisplay (expected 0, found 3840)
<7> [994.729429] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_htotal (expected 0, found 4000)
<7> [994.730112] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_hblank_start (expected 0, found 3840)
<7> [994.730218] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_hblank_end (expected 0, found 4000)
<7> [994.730323] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_hsync_start (expected 0, found 3888)
<7> [994.730427] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_hsync_end (expected 0, found 3920)
<7> [994.730552] xe 0000:03:00.0: [drm:pipe_config_mismatch [xe]] [CRTC:131:pipe B] fastset requirement not met in hw.pipe_mode.crtc_vdisplay (expected 0, found 2160)