igt@kms_pipe_crc_basic@* - dmesg-fail/incomplete/timeout - mmio request * no reply
<6> [923.010956] xe 0000:03:00.0: [drm] 0xffffffff 0xffffffff 0xffffffff 0xffffffff
<6> [923.010959] xe 0000:03:00.0: [drm] 0xffffffff 0xffffffff 0xffffffff 0xffffffff
<6> [923.010962] xe 0000:03:00.0: [drm] 0xffffffff 0xffffffff 0xffffffff 0xffffffff
<6> [923.010966] xe 0000:03:00.0: [drm] 0xffffffff 0xffffffff 0xffffffff 0xffffffff
<6> [923.010969] xe 0000:03:00.0: [drm] 0xffffffff 0xffffffff 0xffffffff 0xffffffff
<3> [923.071301] xe 0000:03:00.0: [drm] *ERROR* mmio request 0x508: no reply 0x508
<3> [923.071403] xe 0000:03:00.0: [drm] *ERROR* Failed to enable CT (-110)
<3> [923.071422] xe 0000:03:00.0: [drm] *ERROR* GT0: resume failed (-ETIMEDOUT)
<7> [923.071470] xe 0000:03:00.0: [drm:intel_power_well_enable [xe]] enabling always-on
<7> [923.071593] xe 0000:03:00.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [923.071819] xe 0000:03:00.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 01 to 00
<7> [923.073353] [drm:drm_mode_setcrtc [drm]] [CRTC:80:pipe A]
<7> [923.081443] [drm:drm_mode_setcrtc [drm]] [CRTC:131:pipe B]
<7> [923.081539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:264:DP-3]
<7> [923.081940] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:264:DP-3] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [923.082074] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link computation with max lane count 4 max rate 810000 max bpp 30 pixel clock 537600KHz
<7> [923.082182] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp 30
<7> [923.082289] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link rate required 2016000 available 2160000
<7> [923.082395] xe 0000:03:00.0: [drm:intel_dp_compute_config [xe]] [CONNECTOR:264:DP-3] SDP split enable: no