Many KMS testcases - dmesg-fail/dmesg-warn/incomplete/abort - *ERROR* CPU pipe [ABCD] FIFO underrun: port,transcoder
<7> [899.742898] xe 0000:03:00.0: [drm:verify_connector_state [xe]] [CONNECTOR:264:DP-3]
<7> [899.743353] xe 0000:03:00.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:80:pipe A]
<7> [899.743860] xe 0000:03:00.0: [drm:intel_ddi_get_config [xe]] [ENCODER:263:DDI C/PHY C] Fec status: 0
<7> [899.748444] xe 0000:03:00.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe A
<7> [899.749844] xe 0000:03:00.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe A
<3> [899.793982] xe 0000:03:00.0: [drm] *ERROR* CPU pipe A FIFO underrun: port,transcoder,
<7> [899.794312] xe 0000:03:00.0: [drm:intel_fbc_underrun_work_fn [xe]] Disabling FBC due to FIFO underrun.
<7> [899.809307] xe 0000:03:00.0: [drm:__intel_fbc_disable [xe]] Disabling FBC on [PLANE:31:plane 1A]
<7> [899.848163] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:264:DP-3] Limiting display bpp to 24 (EDID bpp 30, max requested bpp 24, max platform bpp 36)
<7> [899.848320] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz
<7> [899.848454] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp 24
<7> [899.848581] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP link rate required 1599750 available 2160000
<7> [899.848708] xe 0000:03:00.0: [drm:intel_dp_compute_config [xe]] [CONNECTOR:264:DP-3] SDP split enable: no
<7> [899.848839] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:80:pipe A] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [899.848970] xe 0000:03:00.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:263:DDI C/PHY C] [CRTC:80:pipe A]