<6> [314.878183] [IGT] kms_vblank: starting subtest accuracy-idle
<6> [314.878967] [IGT] kms_vblank: starting dynamic subtest pipe-A-eDP-1
<7> [314.879898] xe 0000:00:02.0: [drm:drm_mode_addfb2 [drm]] [FB:228]
<7> [314.880041] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [314.880128] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [314.964038] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CRTC:82:pipe A]
<7> [314.964250] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CONNECTOR:189:eDP-1]
<7> [314.979695] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [314.980073] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [314.980373] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<7> [315.887566] xe 0000:00:02.0: [drm:intel_tc_port_update_mode [xe]] Port F/TC#3: TC port mode reset (tbt-alt -> disconnected)
<7> [315.887713] xe 0000:00:02.0: [drm:intel_tc_port_update_mode [xe]] Port E/TC#2: TC port mode reset (tbt-alt -> disconnected)
<7> [315.887722] xe 0000:00:02.0: [drm:intel_tc_port_update_mode [xe]] Port D/TC#1: TC port mode reset (tbt-alt -> disconnected)
<4> [316.144952] xe 0000:00:02.0: [drm] GT1: G2H fence (19306) not found!
<7> [316.176919] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [316.177240] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [316.220314] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CRTC:134:pipe B]
<7> [316.226190] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CRTC:186:pipe C]
<7> [316.262893] xe 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe A
<7> [316.283678] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [316.284098] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [316.284433] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<7> [318.063704] xe 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 turning VDD off
<7> [318.064053] xe 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
<7> [318.296414] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CRTC:82:pipe A]
<7> [318.296789] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.enable (expected yes, found no)
<7> [318.297192] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [318.297549] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in cpu_transcoder (expected 0, found -1)
<7> [318.297904] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in lane_count (expected 4, found 0)
<7> [318.298257] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in dp_m_n (expected tu 64 data 6329869/8388608 link 421991/524288, found tu 0, data 0/0 link 0/0)
<7> [318.298711] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in output_types (expected 0x00000100, found 0x00000000)
<7> [318.299101] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in framestart_delay (expected 1, found 0)
<7> [318.299575] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hdisplay (expected 2880, found 0)
<7> [318.299944] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_htotal (expected 3040, found 0)
<7> [318.300361] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hblank_start (expected 2880, found 0)
<7> [318.300766] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hblank_end (expected 3040, found 0)
<7> [318.301121] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hsync_start (expected 2928, found 0)
<7> [318.301473] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hsync_end (expected 2960, found 0)
<7> [318.301864] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vdisplay (expected 1800, found 0)
<7> [318.302221] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vblank_start (expected 1800, found 0)
<7> [318.302635] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vsync_start (expected 1803, found 0)
<7> [318.302998] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vsync_end (expected 1809, found 0)
<7> [318.303338] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vtotal (expected 1906, found 0)
<7> [318.303764] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vblank_end (expected 1906, found 0)
<7> [318.304116] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_hdisplay (expected 2880, found 0)
<7> [318.304467] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_htotal (expected 3040, found 0)
<7> [318.304860] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_hblank_start (expected 2880, found 0)
<7> [318.305198] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_hblank_end (expected 3040, found 0)
<7> [318.305534] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_hsync_start (expected 2928, found 0)
<7> [318.305866] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_hsync_end (expected 2960, found 0)
<7> [318.306196] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_vdisplay (expected 1800, found 0)
<7> [318.306530] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_vblank_start (expected 1800, found 0)
<7> [318.306859] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_vsync_start (expected 1803, found 0)
<7> [318.307152] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_vsync_end (expected 1809, found 0)
<7> [318.307467] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_vtotal (expected 1906, found 0)
<7> [318.307769] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_vblank_end (expected 1906, found 0)
<7> [318.308057] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in pixel_multiplier (expected 1, found 0)
<7> [318.308320] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.flags (2) (expected 2, found 0)
<7> [318.308584] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.flags (8) (expected 8, found 0)
<7> [318.308848] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in pipe_bpp (expected 30, found 0)
<7> [318.309103] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.pipe_mode.crtc_clock (expected 347710, found 0)
<7> [318.309338] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.adjusted_mode.crtc_clock (expected 347710, found 0)
<7> [318.309616] xe 0000:00:02.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in port_clock (expected 432000, found 0)
<7> [318.309859] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] fastset requirement not met, forcing full modeset
<7> [318.310177] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] Enabled dbuf slices 0xf -> 0x1 (total dbuf slices 0xf), mbus joined? yes->no
<7> [318.310376] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [CRTC:82:pipe A] dbuf slices 0xf -> 0x0, ddb (0 - 4096) -> (0 - 0), active pipes 0x1 -> 0x0
<7> [318.310689] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] ddb ( 0 - 4054) -> ( 0 - 0), size 4054 -> 0
<7> [318.310865] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:77:cursor A] ddb (4054 - 4096) -> ( 0 - 0), size 42 -> 0
<7> [318.311035] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7,*twm,*swm,*stwm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm
<7> [318.311204] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] lines 1, 12, 12, 12, 11, 12, 0, 0, 0, 3, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [318.311371] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] blocks 24, 289, 289, 289, 265, 289, 0, 0, 38, 73, 87 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [318.311571] xe 0000:00:02.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] min_ddb 28, 319, 319, 319, 293, 319, 0, 0, 39, 82, 88 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [318.311761] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] [CRTC:82:pipe A] data rate 0 num active planes 0
<7> [318.311984] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 0: max bw 23530 required 0 qgv_peak_bw: 38400
<7> [318.312213] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 1: max bw 36260 required 0 qgv_peak_bw: 38400
<7> [318.312410] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 2: max bw 38000 required 0 qgv_peak_bw: 38400
<7> [318.312584] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] QGV point 3: max bw 38000 required 0 qgv_peak_bw: 38400
<7> [318.312746] xe 0000:00:02.0: [drm:intel_bw_atomic_check [xe]] Matching peaks QGV bw: 38400 for required data rate: 0
<7> [318.312914] xe 0000:00:02.0: [drm:intel_modeset_calc_cdclk [xe]] Can change cdclk via squashing
<7> [318.313077] xe 0000:00:02.0: [drm:intel_modeset_calc_cdclk [xe]] New cdclk calculated to be logical 153600 kHz, actual 153600 kHz
<7> [318.313230] xe 0000:00:02.0: [drm:intel_modeset_calc_cdclk [xe]] New voltage level calculated to be logical 0, actual 0
<7> [318.313413] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [CRTC:82:pipe A] enable: no [modeset]
<7> [318.313604] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:32:plane 1A] fb: [NOFB], visible: no
<7> [318.313776] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:41:plane 2A] fb: [NOFB], visible: no
<7> [318.313924] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:50:plane 3A] fb: [NOFB], visible: no
<7> [318.314067] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:59:plane 4A] fb: [NOFB], visible: no
<7> [318.314219] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:68:plane 5A] fb: [NOFB], visible: no
<7> [318.314361] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:77:cursor A] fb: [NOFB], visible: no
<7> [318.314570] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [318.314715] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [318.314902] xe 0000:00:02.0: [drm:intel_psr_disable_locked [xe]] Disabling PSR2
<7> [318.331657] xe 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 turning VDD on
<7> [318.331774] xe 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
<7> [318.344519] xe 0000:00:02.0: [drm:intel_edp_backlight_off [xe]]
<7> [318.551825] xe 0000:00:02.0: [drm:intel_backlight_set_pwm_level [xe]] [CONNECTOR:189:eDP-1] set backlight PWM = 0
<7> [318.552453] xe 0000:00:02.0: [drm:intel_disable_transcoder [xe]] disabling pipe A
<7> [318.563918] xe 0000:00:02.0: [drm:intel_pps_off_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 turn panel power off
<7> [318.564303] xe 0000:00:02.0: [drm:intel_pps_off_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 wait for panel power off time
<7> [318.564658] xe 0000:00:02.0: [drm:wait_panel_status [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 mask: 0xb0000000 value: 0x00000000 PP_STATUS: 0xa0000002 PP_CONTROL: 0x00000060
<7> [318.647845] xe 0000:00:02.0: [drm:wait_panel_status [xe]] Wait complete
<7> [318.648279] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling AUX_A
<7> [318.648627] xe 0000:00:02.0: [drm:__intel_fbc_disable [xe]] Disabling FBC on [PLANE:32:plane 1A]
<7> [318.649167] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:188:DDI A/PHY A]
<7> [318.649421] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:197:DDI TC1/PHY TC1]
<7> [318.649661] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:199:DP-MST A]
<7> [318.649889] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:200:DP-MST B]
<7> [318.650156] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:201:DP-MST C]
<7> [318.650382] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:209:DDI TC2/PHY TC2]
<7> [318.650639] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:211:DP-MST A]
<7> [318.650865] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:212:DP-MST B]
<7> [318.651091] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:213:DP-MST C]
<7> [318.651313] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:217:DDI TC3/PHY TC3]
<7> [318.651659] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:219:DP-MST A]
<7> [318.651906] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:220:DP-MST B]
<7> [318.652150] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:221:DP-MST C]
<7> [318.652417] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:189:eDP-1]
<7> [318.652713] xe 0000:00:02.0: [drm:intel_dbuf_mdclk_cdclk_ratio_update [xe]] Updating dbuf ratio to 4 (mbus joined: no)
<7> [318.653020] xe 0000:00:02.0: [drm:intel_dbuf_mbus_join_update [xe]] Changing mbus joined: yes -> no (pipe: *)
<7> [318.653275] xe 0000:00:02.0: [drm:intel_set_cdclk [xe]] Post changing CDCLK to 153600 kHz, VCO 614400 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [318.653640] xe 0000:00:02.0: [drm:intel_dbuf_mdclk_cdclk_ratio_update [xe]] Updating dbuf ratio to 4 (mbus joined: no)
<7> [318.653959] xe 0000:00:02.0: [drm:intel_audio_cdclk_change_post.part.0 [xe]] aud_ts_cdclk set to M=60, N=384
<7> [318.654303] xe 0000:00:02.0: [drm:gen9_dbuf_slices_update [xe]] Updating dbuf slices to 0x1