Stdout
Using IGT_SRANDOM=1722499508 for randomisation
Opened device: /dev/dri/card0
Starting subtest: s3-d3hot-basic-exec
[cmd] rtcwake: wakeup from "mem" using /dev/rtc0 at Thu Aug 1 08:05:25 2024
Stderr
Starting subtest: s3-d3hot-basic-exec
Dmesg
<6> [1518.941498] Console: switching to colour dummy device 80x25
<6> [1518.941807] [IGT] xe_pm: executing
<6> [1518.975519] [IGT] xe_pm: starting subtest s3-d3hot-basic-exec
<7> [1518.975676] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:260:DP-2] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [1518.975794] xe 0000:03:00.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:259:DDI TC2/PHY G][CRTC:82:pipe A] DP link limits: pixel clock 533250 kHz DSC off max lanes 4 max rate 540000 max pipe_bpp 30 max link_bpp 30.0000
<7> [1518.975878] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp input 30 compressed 0.0000 link rate required 1999688 available 2160000
<7> [1518.975957] xe 0000:03:00.0: [drm:intel_psr_compute_config [xe]] PSR disabled by flag
<7> [1518.976027] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 30, dithering: 0
<7> [1518.976109] xe 0000:03:00.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:259:DDI TC2/PHY G] [CRTC:82:pipe A]
<7> [1518.976201] xe 0000:03:00.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [1518.976286] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] fastset requirement not met, forcing full modeset
<7> [1518.976488] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:260:DP-2] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [1518.976586] xe 0000:03:00.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:259:DDI TC2/PHY G][CRTC:82:pipe A] DP link limits: pixel clock 533250 kHz DSC off max lanes 4 max rate 540000 max pipe_bpp 30 max link_bpp 30.0000
<7> [1518.976669] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp input 30 compressed 0.0000 link rate required 1999688 available 2160000
<7> [1518.976746] xe 0000:03:00.0: [drm:intel_psr_compute_config [xe]] PSR disabled by flag
<7> [1518.976828] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 30, dithering: 0
<7> [1518.976913] xe 0000:03:00.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:259:DDI TC2/PHY G] [CRTC:82:pipe A]
<7> [1518.977007] xe 0000:03:00.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [1518.977116] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] fastset requirement not met, forcing full modeset
<7> [1518.977241] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] Enabled dbuf slices 0xf -> 0xd (total dbuf slices 0xf), mbus joined? no->no
<7> [1518.977333] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [CRTC:82:pipe A] dbuf slices 0x3 -> 0x0, ddb (0 - 2048) -> (0 - 0), active pipes 0x7 -> 0x6
<7> [1518.977580] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CONNECTOR:260:DP-2] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [1518.977722] xe 0000:03:00.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:259:DDI TC2/PHY G][CRTC:82:pipe A] DP link limits: pixel clock 533250 kHz DSC off max lanes 4 max rate 540000 max pipe_bpp 30 max link_bpp 30.0000
<7> [1518.977803] xe 0000:03:00.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 540000 bpp input 30 compressed 0.0000 link rate required 1999688 available 2160000
<7> [1518.977875] xe 0000:03:00.0: [drm:intel_psr_compute_config [xe]] PSR disabled by flag
<7> [1518.977935] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] hw max bpp: 30, pipe bpp: 30, dithering: 0
<7> [1518.978007] xe 0000:03:00.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:259:DDI TC2/PHY G] [CRTC:82:pipe A]
<7> [1518.978180] xe 0000:03:00.0: [drm:intel_pipe_config_compare [xe]] [CRTC:82:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [1518.978419] xe 0000:03:00.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] fastset requirement not met, forcing full modeset
<7> [1518.978683] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] Enabled dbuf slices 0xf -> 0xd (total dbuf slices 0xf), mbus joined? no->no
<7> [1518.978860] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [CRTC:82:pipe A] dbuf slices 0x3 -> 0x0, ddb (0 - 2048) -> (0 - 0), active pipes 0x7 -> 0x6
<7> [1518.979120] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] ddb ( 0 - 1933) -> ( 0 - 0), size 1933 -> 0
<7> [1518.979286] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [PLANE:77:cursor A] ddb (1933 - 2048) -> ( 0 - 0), size 115 -> 0
<7> [1518.979455] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7,*twm,*swm,*stwm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm, stwm
<7> [1518.979517] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] lines 2, 6, 14, 20, 34, 34, 34, 34, 0, 29, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [1518.979568] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] blocks 63, 187, 435, 621,1055,1055,1055,1055, 77, 900, 914 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [1518.979616] xe 0000:03:00.0: [drm:skl_compute_wm [xe]] [PLANE:32:plane 1A] min_ddb 71, 207, 480, 685,1162,1162, 0, 0, 78, 991, 991 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [1518.979663] xe 0000:03:00.0: [drm:intel_bw_atomic_check [xe]] [CRTC:82:pipe A] data rate 0 num active planes 0
<7> [1518.979730] xe 0000:03:00.0: [drm:intel_bw_atomic_check [xe]] QGV point 0: max bw 33600 required 2749 qgv_peak_bw: 48000
<7> [1518.979795] xe 0000:03:00.0: [drm:intel_bw_atomic_check [xe]] QGV point 1: max bw 53000 required 2749 qgv_peak_bw: 48000
<7> [1518.979859] xe 0000:03:00.0: [drm:intel_bw_atomic_check [xe]] Matching peaks QGV bw: 48000 for required data rate: 2749
<7> [1518.979934] xe 0000:03:00.0: [drm:intel_modeset_calc_cdclk [xe]] New cdclk calculated to be logical 652800 kHz, actual 652800 kHz
<7> [1518.979998] xe 0000:03:00.0: [drm:intel_modeset_calc_cdclk [xe]] New voltage level calculated to be logical 3, actual 3
<7> [1518.980074] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] [CRTC:82:pipe A] enable: yes [modeset]
<7> [1518.980141] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] active: no, output_types: DP (0x80), output format: RGB, sink format: RGB
<7> [1518.980206] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] cpu_transcoder: A, pipe bpp: 30, dithering: 0
<7> [1518.980270] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] MST master transcoder: <invalid>
<7> [1518.980341] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [1518.980426] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] joiner: no, pipes: 0x0
<7> [1518.980504] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] splitter: disabled, link count 0, overlap 0
<7> [1518.980576] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] dp m_n: lanes: 4; data_m: 7766017, data_n: 8388608, link_m: 517734, link_n: 524288, tu: 64
<7> [1518.980640] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] dp m2_n2: lanes: 4; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [1518.980702] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] fec: disabled, enhanced framing: enabled
<7> [1518.980764] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] sdp split: disabled
<7> [1518.980828] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] psr: disabled, selective update: disabled, panel replay: disabled, selective fetch: disabled
<7> [1518.980892] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] framestart delay: 1, MSA timing delay: 0
<7> [1518.980962] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] audio: 1, infoframes: 0, infoframes enabled: 0x0
<7> [1518.981027] ELD: 10 00 08 00 6c 14 00 01 00 00 00 00 00 00 00 00
<7> [1518.981028] ELD: 1e 6d c2 5b 4c 47 20 55 4c 54 52 41 46 49 4e 45
<7> [1518.981029] ELD: 09 07 07 00
<7> [1518.981030] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] vrr: no, vmin: 0, vmax: 0, pipeline full: 0, guardband: 0 flipline: 0, vmin vblank: 1, vmax vblank: 0
<7> [1518.981093] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] requested mode: "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
<7> [1518.981155] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] adjusted mode: "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
<7> [1518.981217] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] crtc timings: clock=533250, hd=3840 hb=3840-4000 hs=3888-3920 ht=4000, vd=2160 vb=2160-2222 vs=2163-2168 vt=2222, flags=0x9
<7> [1518.981279] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] pipe mode: "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x40 0x9
<7> [1518.981341] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] crtc timings: clock=533250, hd=3840 hb=3840-4000 hs=3888-3920 ht=4000, vd=2160 vb=2160-2222 vs=2163-2168 vt=2222, flags=0x9
<7> [1518.981402] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] port clock: 540000, pipe src: 3840x2160+0+0, pixel rate 533250
<7> [1518.981466] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] linetime: 61, ips linetime: 0
<7> [1518.981530] xe 0000:03:00.0: [drm:intel_crtc_state_dump [xe]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0