igt@kms_flip@*flip-vs-suspend-*@* - incomplete - PM: suspend entry (deep)
<7> [146.014849] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:261:DP-MST A]
<7> [146.014899] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:262:DP-MST B]
<7> [146.014948] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:263:DP-MST C]
<7> [146.014997] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:264:DP-MST D]
<7> [146.015047] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:271:DDI TC3/PHY H]
<7> [146.015094] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:275:DDI TC4/PHY I]
<7> [146.015141] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:277:DP-MST A]
<7> [146.015186] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:278:DP-MST B]
<7> [146.015233] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:279:DP-MST C]
<7> [146.015282] xe 0000:03:00.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:280:DP-MST D]
<7> [146.015331] xe 0000:03:00.0: [drm:gen9_dbuf_slices_update [xe]] Updating dbuf slices to 0xf
<7> [146.015456] xe 0000:03:00.0: [drm:intel_dbuf_mdclk_cdclk_ratio_update [xe]] Updating dbuf ratio to 2 (mbus joined: no)
<7> [146.017453] xe 0000:03:00.0: [drm:intel_power_well_enable [xe]] enabling AUX_TC2
<7> [146.020511] xe 0000:03:00.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX USBC2/DDI TC2/PHY G: DPCD: 12 14 c4 01 01 15 01 81 00 01 04 01 0f 00 01
<7> [146.026399] xe 0000:03:00.0: [drm:intel_dp_init_lttpr_and_dprx_caps [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] LTTPR common capabilities: 00 00 00 00 00 00 00 00
<7> [146.027499] xe 0000:03:00.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX USBC2/DDI TC2/PHY G: DPCD: 12 14 c4 01 01 15 01 81 00 01 04 01 0f 00 01
<7> [146.027840] xe 0000:03:00.0: [drm:intel_dp_start_link_train [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] Using LINK_BW_SET value 0a
<7> [146.029272] xe 0000:03:00.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [146.029554] xe 0000:03:00.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] Using DP training pattern TPS1
<7> [146.038198] xe 0000:03:00.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] Clock recovery OK
<7> [146.038420] xe 0000:03:00.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] Using DP training pattern TPS3
<7> [146.045977] xe 0000:03:00.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] Channel EQ done. DP Training successful
<7> [146.046326] xe 0000:03:00.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G][DPRX] Link Training passed at link rate = 270000, lane count = 4
<7> [146.047104] xe 0000:03:00.0: [drm:intel_enable_transcoder [xe]] enabling pipe B
<7> [146.064389] xe 0000:03:00.0: [drm:intel_audio_codec_enable [xe]] [CONNECTOR:260:DP-2][ENCODER:259:DDI TC2/PHY G] Enable audio codec on [CRTC:134:pipe B], 40 bytes ELD
<7> [146.080886] xe 0000:03:00.0: [drm:verify_connector_state [xe]] [CONNECTOR:260:DP-2]
<7> [146.081395] xe 0000:03:00.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:134:pipe B]
<7> [146.153075] xe 0000:03:00.0: [drm:intel_power_well_disable [xe]] disabling AUX_TC2
<6> [146.191788] PM: suspend entry (deep)
<6> [146.192522] Filesystems sync: 0.000 seconds