igt@kms_plane@pixel-format* - warn - CRC mismatches with format *
Stdout
Starting dynamic subtest: pipe-A-plane-3
Dynamic subtest pipe-A-plane-3: SUCCESS (3.987s)
Stderr
Starting dynamic subtest: pipe-A-plane-3
(kms_plane:1350) WARNING: CRC mismatches with format YUYV(0x56595559) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format YUYV(0x56595559) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format YUYV(0x56595559) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format YUYV(0x56595559) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format YUYV(0x56595559) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format YUYV(0x56595559) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format Y210(0x30313259) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format Y210(0x30313259) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format Y210(0x30313259) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format Y210(0x30313259) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format Y210(0x30313259) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format Y210(0x30313259) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format XYUV(0x56555958) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format XYUV(0x56555958) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format XYUV(0x56555958) on A.3 with 1/4 solid colors tested (0x1)
(kms_plane:1350) WARNING: CRC mismatches with format XYUV(0x56555958) on A.3 with 1/4 solid colors tested (0x1)
Dynamic subtest pipe-A-plane-3: SUCCESS (3.987s)
Dmesg
<6> [308.403336] [IGT] kms_plane: starting dynamic subtest pipe-A-plane-3
<7> [308.403523] xe 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe A
<7> [308.403897] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CONNECTOR:241:eDP-1] Limiting display bpp to 24 (EDID bpp 24, max requested bpp 36, max platform bpp 36)
<7> [308.404046] xe 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:240:DDI B/PHY B][CRTC:82:pipe A] DP link limits: pixel clock 138500 kHz DSC off max lanes 2 max rate 540000 max pipe_bpp 24 max link_bpp 24.0000
<7> [308.404167] xe 0000:00:02.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 2 clock 216000 bpp input 24 compressed 0.0000 link rate required 415500 available 432000
<7> [308.404281] xe 0000:00:02.0: [drm:intel_psr_compute_config [xe]] Selective update not enabled because it would inhibit pipe CRC calculation
<7> [308.404381] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CRTC:82:pipe A] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [308.404489] xe 0000:00:02.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:240:DDI B/PHY B] [CRTC:82:pipe A]
<7> [308.404650] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [CRTC:82:pipe A] enable: yes [fastset]
<7> [308.404753] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] active: yes, output_types: EDP (0x100), output format: RGB, sink format: RGB