<7> [423.126867] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [423.127342] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [423.127689] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<7> [423.188589] [drm:drm_mode_setcrtc [drm]] [CRTC:80:pipe A]
<7> [423.188794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:185:eDP-1]
<7> [423.190048] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [423.190258] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [423.226863] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [423.227195] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [423.227453] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<7> [423.286393] xe 0000:00:02.0: [drm:xe_migrate_clear [xe]] Pass 0, size: 8192
<7> [423.290493] xe 0000:00:02.0: [drm:xe_migrate_clear [xe]] Pass 0, size: 4194304
<7> [423.290779] xe 0000:00:02.0: [drm:xe_migrate_clear [xe]] Pass 1, size: 4194304
<7> [423.290967] xe 0000:00:02.0: [drm:xe_migrate_clear [xe]] Pass 2, size: 827392
<3> [423.548765] xe 0000:00:02.0: [drm] *ERROR* GT0: TLB invalidation fence timeout, seqno=4208 recv=4207
<3> [423.549851] xe 0000:00:02.0: [drm] *ERROR* GT0: TLB invalidation fence timeout, seqno=4209 recv=4207
<3> [423.550038] xe 0000:00:02.0: [drm] *ERROR* GT0: TLB invalidation fence timeout, seqno=4210 recv=4207
<7> [423.550580] xe 0000:00:02.0: [drm:xe_migrate_clear [xe]] Pass 0, size: 8192
<7> [423.551787] [drm:drm_mode_setcrtc [drm]] [CRTC:80:pipe A]
<7> [423.552035] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.enable (expected yes, found no)
<7> [423.552043] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.active (expected yes, found no)
<7> [423.552046] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in cpu_transcoder (expected 0, found -1)
<7> [423.552050] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in lane_count (expected 2, found 0)
<7> [423.552053] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in dp_m_n (expected tu 64 data 7392460/8388608 link 308019/524288, found tu 0, data 0/0 link 0/0)
<7> [423.552057] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in output_types (expected 0x00000100, found 0x00000000)
<7> [423.552061] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in framestart_delay (expected 1, found 0)
<7> [423.552063] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hdisplay (expected 1920, found 0)
<7> [423.552066] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_htotal (expected 2080, found 0)
<7> [423.552069] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hblank_start (expected 1920, found 0)
<7> [423.552072] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hblank_end (expected 2080, found 0)
<7> [423.552074] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hsync_start (expected 1968, found 0)
<7> [423.552076] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_hsync_end (expected 2000, found 0)
<7> [423.552078] xe 0000:00:02.0: [drm] [CRTC:80:pipe A] fastset requirement not met in hw.pipe_mode.crtc_vdisplay (expected 1200, found 0)