<7> [372.668612] xe 0000:00:02.0: [drm] requested mode: "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x9
<7> [372.668616] xe 0000:00:02.0: [drm] adjusted mode: "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x9
<7> [372.668618] xe 0000:00:02.0: [drm] crtc timings: clock=148500, hd=1920 hb=1920-2200 hs=2008-2052 ht=2200, vd=1080 vb=1080-1125 vs=1084-1089 vt=1125, flags=0x9
<7> [372.668621] xe 0000:00:02.0: [drm] pipe mode: "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x9
<7> [372.668623] xe 0000:00:02.0: [drm] crtc timings: clock=148500, hd=1920 hb=1920-2200 hs=2008-2052 ht=2200, vd=1080 vb=1080-1125 vs=1084-1089 vt=1125, flags=0x9
<7> [372.668626] xe 0000:00:02.0: [drm] port clock: 270000, pipe src: 1920x1080+0+0, pixel rate 148500
<7> [372.668628] xe 0000:00:02.0: [drm] linetime: 119, ips linetime: 0
<7> [372.668629] xe 0000:00:02.0: [drm] num_scalers: 2, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0
<7> [372.668631] xe 0000:00:02.0: [drm] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [372.668633] xe 0000:00:02.0: [drm] ips: 0, double wide: 0, drrs: 0
<7> [372.668635] xe 0000:00:02.0: [drm] dpll_hw_state: dpll: 0x41eb0, dpll_md: 0x4800be88, fp0: 0x5000000, fp1: 0x5
<7> [372.668637] xe 0000:00:02.0: [drm] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [372.668639] xe 0000:00:02.0: [drm] pre csc lut: 0 entries, post csc lut: 0 entries
<7> [372.668641] xe 0000:00:02.0: [drm] output csc: pre offsets: 0x0000 0x0000 0x0000
<7> [372.668643] xe 0000:00:02.0: [drm] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [372.668645] xe 0000:00:02.0: [drm] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [372.668647] xe 0000:00:02.0: [drm] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [372.668649] xe 0000:00:02.0: [drm] output csc: post offsets: 0x0000 0x0000 0x0000
<7> [372.668650] xe 0000:00:02.0: [drm] pipe csc: pre offsets: 0x0000 0x0000 0x0000
<7> [372.668653] xe 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [372.668655] xe 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [372.668656] xe 0000:00:02.0: [drm] pipe csc: coefficients: 0x0000 0x0000 0x0000
<7> [372.668658] xe 0000:00:02.0: [drm] pipe csc: post offsets: 0x0000 0x0000 0x0000
<7> [372.668660] xe 0000:00:02.0: [drm] [PLANE:133:plane 1C] fb: [FB:186] 2256x1504 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
<7> [372.668663] xe 0000:00:02.0: [drm] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [372.668665] xe 0000:00:02.0: [drm] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0
<7> [372.668667] xe 0000:00:02.0: [drm] [PLANE:142:plane 2C] fb: [NOFB], visible: no
<7> [372.668670] xe 0000:00:02.0: [drm] [PLANE:151:plane 3C] fb: [NOFB], visible: no
<7> [372.668672] xe 0000:00:02.0: [drm] [PLANE:160:plane 4C] fb: [NOFB], visible: no
<7> [372.668674] xe 0000:00:02.0: [drm] [PLANE:169:plane 5C] fb: [NOFB], visible: no
<7> [372.668676] xe 0000:00:02.0: [drm] [PLANE:178:cursor C] fb: [NOFB], visible: no
<7> [372.672377] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_A
<7> [372.672575] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_2
<7> [372.672717] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_B
<7> [372.672853] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PICA_TC
<7> [372.672985] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling PW_C
<7> [372.673149] xe 0000:00:02.0: [drm:intel_pmdemand_program_params [xe]] initate pmdemand request values: (0x18000f1 0xc010e72)
<7> [372.673406] xe 0000:00:02.0: [drm:intel_cdclk_dump_config [xe]] Changing CDCLK to 192000 kHz, VCO 614400 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [372.673556] xe 0000:00:02.0: [drm:intel_audio_cdclk_change_post.part.0 [xe]] aud_ts_cdclk set to M=60, N=480
<7> [372.673658] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:184:DDI A/PHY A]
<7> [372.673727] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:193:DDI TC1/PHY TC1]
<7> [372.673791] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:195:DP-MST A]
<7> [372.673853] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:196:DP-MST B]
<7> [372.673913] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:197:DP-MST C]
<7> [372.673974] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:205:DDI TC2/PHY TC2]
<7> [372.674034] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:207:DP-MST A]
<7> [372.674095] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:208:DP-MST B]
<7> [372.674160] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:209:DP-MST C]
<7> [372.674221] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:213:DDI TC3/PHY TC3]
<7> [372.674281] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:215:DP-MST A]
<7> [372.674343] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:216:DP-MST B]
<7> [372.674411] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:217:DP-MST C]
<7> [372.674477] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:229:DP-6]
<7> [372.674563] xe 0000:00:02.0: [drm:gen9_dbuf_slices_update [xe]] Updating dbuf slices to 0xf
<7> [372.674754] xe 0000:00:02.0: [drm:intel_pps_on_unlocked [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 turn panel power on
<7> [372.674835] xe 0000:00:02.0: [drm:wait_panel_power_cycle [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 wait for panel power cycle
<7> [373.276333] xe 0000:00:02.0: [drm:wait_panel_status [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 mask: 0xb800000f value: 0x00000000 PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
<7> [373.276483] xe 0000:00:02.0: [drm:wait_panel_status [xe]] Wait complete
<7> [373.276566] xe 0000:00:02.0: [drm:intel_pps_on_unlocked [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 wait for panel power on
<7> [373.276660] xe 0000:00:02.0: [drm:wait_panel_status [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 mask: 0xb000000f value: 0x80000008 PP_STATUS: 0x9000000a PP_CONTROL: 0x00000063
<7> [373.284797] xe 0000:00:02.0: [drm:intel_get_hpd_pins [xe]] hotplug event received, stat 0x00010000, dig 0x0000000a, pins 0x00000010, long 0x00000010
<7> [373.284935] xe 0000:00:02.0: [drm:intel_hpd_irq_handler [xe]] digital hpd on [ENCODER:184:DDI A/PHY A] - long
<7> [373.285014] xe 0000:00:02.0: [drm:intel_hpd_irq_handler [xe]] Received HPD interrupt on PIN 4 - cnt: 20
<7> [373.285208] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] ignoring long hpd on eDP [ENCODER:184:DDI A/PHY A]
<7> [373.286875] xe 0000:00:02.0: [drm:intel_get_hpd_pins [xe]] hotplug event received, stat 0x00010000, dig 0x0000000a, pins 0x00000010, long 0x00000010
<7> [373.286958] xe 0000:00:02.0: [drm:intel_hpd_irq_handler [xe]] digital hpd on [ENCODER:184:DDI A/PHY A] - long
<7> [373.287017] xe 0000:00:02.0: [drm:intel_hpd_irq_handler [xe]] Received HPD interrupt on PIN 4 - cnt: 30
<7> [373.287201] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] ignoring long hpd on eDP [ENCODER:184:DDI A/PHY A]
<7> [373.360059] xe 0000:00:02.0: [drm:intel_get_hpd_pins [xe]] hotplug event received, stat 0x00010000, dig 0x0000000a, pins 0x00000010, long 0x00000010
<7> [373.360178] xe 0000:00:02.0: [drm:intel_hpd_irq_handler [xe]] digital hpd on [ENCODER:184:DDI A/PHY A] - long
<7> [373.360260] xe 0000:00:02.0: [drm:intel_hpd_irq_handler [xe]] Received HPD interrupt on PIN 4 - cnt: 40
<7> [373.360371] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] ignoring long hpd on eDP [ENCODER:184:DDI A/PHY A]
<7> [373.534613] xe 0000:00:02.0: [drm:wait_panel_status [xe]] Wait complete
<7> [373.536634] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling AUX_A
<7> [373.538437] xe 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 turning VDD on
<7> [373.538584] xe 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
<7> [373.540630] xe 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: DPCD: 14 00 84 41 00 00 01 80 02 36 00 00 00 08 01
<7> [373.541816] xe 0000:00:02.0: [drm:intel_dp_start_link_train [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Reloading eDP link rates
<7> [373.542537] xe 0000:00:02.0: [drm:intel_dp_start_link_train [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Using LINK_RATE_SET value 00
<7> [373.543233] xe 0000:00:02.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [373.544024] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Using DP training pattern TPS1
<7> [373.545126] xe 0000:00:02.0: [drm:intel_dp_get_adjust_train [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 2/2/0/0, pre-emphasis request: 1/1/0/0
<7> [373.545191] xe 0000:00:02.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 2/2/0/0, pre-emphasis levels: 1/1/0/0
<7> [373.547118] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Clock recovery OK
<7> [373.547183] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Using DP training pattern TPS2
<7> [373.553629] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Channel EQ done. DP Training successful
<7> [373.553732] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:185:eDP-1][ENCODER:184:DDI A/PHY A][DPRX] Link Training passed at link rate = 216000, lane count = 4
<7> [373.554288] xe 0000:00:02.0: [drm:intel_enable_transcoder [xe]] enabling pipe A
<7> [373.554437] xe 0000:00:02.0: [drm:intel_edp_backlight_on [xe]]
<7> [373.554506] xe 0000:00:02.0: [drm:intel_backlight_enable [xe]] pipe A
<7> [373.554582] xe 0000:00:02.0: [drm:intel_backlight_set_pwm_level [xe]] [CONNECTOR:185:eDP-1] set backlight PWM = 13892
<7> [373.554923] xe 0000:00:02.0: [drm:intel_tc_port_update_mode [xe]] Port D/TC#1: TC port mode reset (disconnected -> dp-alt)
<7> [373.554997] xe 0000:00:02.0: [drm:intel_mst_pre_enable_dp [xe]] active links 0
<7> [373.555088] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling AUX_TC1
<7> [373.556914] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_port.part.0 [drm_display_helper]] port ffff88810c161000 (2)
<7> [373.616519] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] got hpd irq on [ENCODER:193:DDI TC1/PHY TC1] - short
<7> [373.618528] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 10 00 00
<7> [373.619677] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_mstb [drm_display_helper]] mstb ffff88810e32e580 (2)
<7> [373.619703] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_mstb [drm_display_helper]] mstb ffff88810e32e580 (1)
<7> [373.619754] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_port [drm_display_helper]] port ffff88810c161000 (1)
<7> [373.621688] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 00 00 00
<7> [373.626336] xe 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX USBC1/DDI TC1/PHY TC1: DPCD: 12 0a c4 01 00 05 01 83 02 00 00 00 00 00 04
<7> [373.632968] xe 0000:00:02.0: [drm:intel_dp_init_lttpr_and_dprx_caps [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] LTTPR common capabilities: 20 1e 80 aa 04 00 01 03
<7> [373.637350] xe 0000:00:02.0: [drm:intel_dp_init_lttpr_and_dprx_caps [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] PHY capabilities: 04 03 00
<7> [373.639415] xe 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX USBC1/DDI TC1/PHY TC1: DPCD: 12 0a c4 01 00 05 01 83 02 00 00 00 00 00 04
<7> [373.640168] xe 0000:00:02.0: [drm:intel_dp_start_link_train [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] Using LINK_BW_SET value 0a
<7> [373.641510] xe 0000:00:02.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [373.642078] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] Using DP training pattern TPS1
<7> [373.646401] xe 0000:00:02.0: [drm:intel_dp_get_adjust_train [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] 8b/10b, lanes: 4, vswing request: 2/2/2/2, pre-emphasis request: 0/0/0/0
<7> [373.646549] xe 0000:00:02.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] 8b/10b, lanes: 4, vswing levels: 2/2/2/2, pre-emphasis levels: 0/0/0/0
<7> [373.651038] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] Clock recovery OK
<7> [373.653692] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] Using DP training pattern TPS4
<7> [373.687352] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] Channel EQ done. DP Training successful
<7> [373.687491] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][LTTPR 1] Link Training passed at link rate = 270000, lane count = 4
<7> [373.689134] xe 0000:00:02.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [373.689252] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] Using DP training pattern TPS1
<7> [373.726030] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] Clock recovery OK
<7> [373.726158] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] Using DP training pattern TPS3
<7> [373.760138] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] Channel EQ done. DP Training successful
<7> [373.760298] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:194:DP-1][ENCODER:193:DDI TC1/PHY TC1][DPRX] Link Training passed at link rate = 270000, lane count = 4
<7> [373.762472] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_port.part.0 [drm_display_helper]] port ffff88810c161000 (2)
<7> [373.767494] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_port [drm_display_helper]] port ffff88810c161000 (1)
<7> [373.767560] xe 0000:00:02.0: [drm:intel_mst_enable_dp [xe]] active links 1
<7> [373.771567] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_port.part.0 [drm_display_helper]] port ffff88810c161000 (2)
<7> [373.771595] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_mstb [drm_display_helper]] mstb ffff88810e32e580 (2)
<7> [373.828311] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] got hpd irq on [ENCODER:193:DDI TC1/PHY TC1] - short
<7> [373.831967] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 10 00 00
<7> [373.835898] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_mstb [drm_display_helper]] mstb ffff88810e32e580 (3)
<7> [373.835949] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_mstb [drm_display_helper]] mstb ffff88810e32e580 (2)
<7> [373.836027] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_mstb [drm_display_helper]] mstb ffff88810e32e580 (1)
<7> [373.836048] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_port [drm_display_helper]] port ffff88810c161000 (1)
<7> [373.836069] xe 0000:00:02.0: [drm:intel_enable_transcoder [xe]] enabling pipe B
<7> [373.836398] xe 0000:00:02.0: [drm:intel_mst_pre_enable_dp [xe]] active links 1
<7> [373.836509] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_port.part.0 [drm_display_helper]] port ffff88812c5bc000 (2)
<7> [373.841042] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 10 00 00
<7> [373.845014] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_mstb [drm_display_helper]] mstb ffff88810e32e580 (2)
<7> [373.845054] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_mstb [drm_display_helper]] mstb ffff88810e32e580 (1)
<7> [373.845127] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_port [drm_display_helper]] port ffff88812c5bc000 (1)
<7> [373.845157] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_port.part.0 [drm_display_helper]] port ffff88812c5bc000 (2)
<7> [373.851812] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 00 00 00
<7> [373.855367] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_port [drm_display_helper]] port ffff88812c5bc000 (1)
<7> [373.855445] xe 0000:00:02.0: [drm:intel_mst_enable_dp [xe]] active links 2
<7> [373.859073] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_port.part.0 [drm_display_helper]] port ffff88812c5bc000 (2)
<7> [373.859113] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_mstb [drm_display_helper]] mstb ffff88810e32e580 (2)
<7> [373.916289] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] got hpd irq on [ENCODER:193:DDI TC1/PHY TC1] - short
<7> [373.919945] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 10 00 00
<7> [373.923839] xe 0000:00:02.0: [drm:drm_dp_mst_topology_try_get_mstb [drm_display_helper]] mstb ffff88810e32e580 (3)
<7> [373.923877] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_mstb [drm_display_helper]] mstb ffff88810e32e580 (2)
<7> [373.923943] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_mstb [drm_display_helper]] mstb ffff88810e32e580 (1)
<7> [373.923962] xe 0000:00:02.0: [drm:drm_dp_mst_topology_put_port [drm_display_helper]] port ffff88812c5bc000 (1)
<7> [373.923984] xe 0000:00:02.0: [drm:intel_enable_transcoder [xe]] enabling pipe C
<7> [373.924675] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] reserved 9240576 bytes of contiguous stolen space for FBC, limit: 2
<7> [373.924791] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] Enabling FBC on [PLANE:31:plane 1A]
<7> [373.925190] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] reserved 6635520 bytes of contiguous stolen space for FBC, limit: 2
<7> [373.925291] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] Enabling FBC on [PLANE:82:plane 1B]
<7> [373.925658] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] reserved 6635520 bytes of contiguous stolen space for FBC, limit: 2
<7> [373.925765] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] Enabling FBC on [PLANE:133:plane 1C]
<7> [373.928591] xe 0000:00:02.0: [drm:intel_dp_hpd_pulse [xe]] DPRX ESI: 02 00 00 00
<7> [373.940978] xe 0000:00:02.0: [drm:gen9_dbuf_slices_update [xe]] Updating dbuf slices to 0xf
<7> [373.941395] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:185:eDP-1]
<7> [373.941525] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:80:pipe A]
<7> [373.943176] xe 0000:00:02.0: [drm:intel_audio_codec_enable [xe]] [CONNECTOR:223:DP-4][ENCODER:196:DP-MST B] Enable audio codec on [CRTC:131:pipe B], 32 bytes ELD
<7> [373.953100] xe 0000:00:02.0: [drm:hsw_audio_config_update [xe]] using automatic Maud, Naud
<7> [373.953397] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:223:DP-4]
<7> [373.953498] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:131:pipe B]
<7> [373.958566] xe 0000:00:02.0: [drm:intel_audio_codec_enable [xe]] [CONNECTOR:221:DP-5][ENCODER:197:DP-MST C] Enable audio codec on [CRTC:182:pipe C], 36 bytes ELD
<7> [373.974305] xe 0000:00:02.0: [drm:hsw_audio_config_update [xe]] using automatic Maud, Naud
<7> [373.974643] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:221:DP-5]
<7> [373.974763] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:182:pipe C]
<7> [374.032276] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling AUX_TC1
<7> [376.568369] xe 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 turning VDD off
<7> [376.568520] xe 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [xe]] [ENCODER:184:DDI A/PHY A] PPS 0 PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
<7> [376.568595] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling AUX_A
<7> [377.010485] xe 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe A
<7> [377.010585] xe 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe B
<7> [377.010645] xe 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe C
<6> [377.215747] PM: suspend entry (s2idle)
<6> [377.215993] Filesystems sync: 0.000 seconds