<7> [219.825780] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: pre offsets: 0x0000 0x0000 0x0000
<7> [219.825931] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: coefficients: 0x7800 0x3000 0x3000
<7> [219.826082] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: coefficients: 0x3000 0x7800 0x3000
<7> [219.826233] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: coefficients: 0x3000 0x3000 0x7800
<7> [219.826381] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: post offsets: 0x0000 0x0000 0x0000
<7> [219.826530] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:84:plane 1B] fb: [FB:227] 2880x1800 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
<7> [219.826683] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [219.826833] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] src: 2880.000000x1800.000000+0.000000+0.000000 dst: 2880x1800+0+0
<7> [219.830332] xe 0000:00:02.0: [drm:intel_psr_disable_locked [xe]] Disabling PSR2
<3> [219.850286] xe 0000:00:02.0: [drm] *ERROR* The master control interrupt lied (DE PIPE)!
<7> [219.850416] xe 0000:00:02.0: [drm:intel_psr_post_plane_update [xe]] Enabling PSR1
<7> [219.852062] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:189:eDP-1]
<7> [219.852508] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:134:pipe B]
<7> [219.883067] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [219.883572] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [219.883988] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<7> [219.900459] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CONNECTOR:189:eDP-1] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [219.900921] xe 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:188:DDI A/PHY A][CRTC:134:pipe B] DP link limits: pixel clock 347710 kHz DSC off max lanes 4 max rate 810000 max pipe_bpp 30 max link_bpp 30.0000
<7> [219.901266] xe 0000:00:02.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 432000 bpp input 30 compressed 0.0000 link rate required 1303913 available 1728000
<7> [219.901606] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CRTC:134:pipe B] hw max bpp: 30, pipe bpp: 30, dithering: 0
<7> [219.901960] xe 0000:00:02.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:188:DDI A/PHY A] [CRTC:134:pipe B]
<7> [219.902486] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [CRTC:134:pipe B] enable: yes [fastset]
<7> [219.902852] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] active: yes, output_types: EDP (0x100), output format: RGB, sink format: RGB
<7> [219.903255] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] cpu_transcoder: B, pipe bpp: 30, dithering: 0
<7> [219.903612] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] MST master transcoder: <invalid>
<7> [219.903962] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [219.904312] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] joiner: no, pipes: 0x0
<7> [219.904660] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] splitter: disabled, link count 0, overlap 0
<7> [219.905011] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dp m_n: lanes: 4; data_m: 6329869, data_n: 8388608, link_m: 421991, link_n: 524288, tu: 64
<7> [219.905362] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dp m2_n2: lanes: 4; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [219.905714] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] fec: disabled, enhanced framing: disabled
<7> [219.906063] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] sdp split: disabled
<7> [219.906407] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] psr: enabled, selective update: enabled, panel replay: disabled, selective fetch: enabled
<7> [219.906752] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] framestart delay: 1, MSA timing delay: 0
<7> [219.907120] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [219.907430] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] DP SDP: VSC, revision 4, length 14
<7> [219.907735] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pixelformat: RGB
<7> [219.908038] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] colorimetry: sRGB
<7> [219.908341] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] bpc: 0
<7> [219.908643] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dynamic range: VESA range
<7> [219.908946] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] content type: Not defined
<7> [219.909250] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] vrr: no, vmin: 1905, vmax: 2859, pipeline full: 0, guardband: 106 flipline: 1906, vmin vblank: 1800, vmax vblank: 2753
<7> [219.909558] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] requested mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906 0x48 0xa
<7> [219.909866] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] adjusted mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906 0x48 0xa
<7> [219.910173] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] crtc timings: clock=347710, hd=2880 hb=2880-3040 hs=2928-2960 ht=3040, vd=1800 vb=1800-1906 vs=1803-1809 vt=1906, flags=0xa
<7> [219.910481] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906 0x40 0xa
<7> [219.910786] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] crtc timings: clock=347710, hd=2880 hb=2880-3040 hs=2928-2960 ht=3040, vd=1800 vb=1800-1906 vs=1803-1809 vt=1906, flags=0xa
<7> [219.911110] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] port clock: 432000, pipe src: 2880x1800+0+0, pixel rate 347710
<7> [219.911416] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] linetime: 70, ips linetime: 0
<7> [219.911719] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0
<7> [219.912021] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [219.912324] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] ips: 0, double wide: 0, drrs: 0
<7> [219.912626] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dpll_hw_state: dpll: 0x69780, dpll_md: 0x42110, fp0: 0x1a2, fp1: 0x1000000
<7> [219.912929] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] csc_mode: 0x80000000 gamma_mode: 0x40000000 gamma_enable: 0 csc_enable: 0
<7> [219.913212] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pre csc lut: 0 entries, post csc lut: 256 entries
<7> [219.913484] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] output csc: pre offsets: 0x0000 0x0000 0x0000
<7> [219.913755] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [219.914025] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [219.914281] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] output csc: coefficients: 0x0000 0x0000 0x0000
<7> [219.914526] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] output csc: post offsets: 0x0000 0x0000 0x0000
<7> [219.914770] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: pre offsets: 0x0000 0x0000 0x0000
<7> [219.915009] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: coefficients: 0x7800 0x3000 0x3000
<7> [219.915236] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: coefficients: 0x3000 0x7800 0x3000
<7> [219.915460] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: coefficients: 0x3000 0x3000 0x7800
<7> [219.915669] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe csc: post offsets: 0x0000 0x0000 0x0000
<7> [219.915876] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [PLANE:84:plane 1B] fb: [FB:227] 2880x1800 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
<7> [219.916089] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] rotation: 0x1, scaler: -1, scaling_filter: 0
<7> [219.916286] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] src: 2880.000000x1800.000000+0.000000+0.000000 dst: 2880x1800+0+0
<7> [219.919885] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [219.920021] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [219.920199] xe 0000:00:02.0: [drm:intel_psr_disable_locked [xe]] Disabling PSR1
<7> [219.933435] xe 0000:00:02.0: [drm:intel_psr_post_plane_update [xe]] Enabling PSR2
<7> [219.935183] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:189:eDP-1]
<7> [219.935507] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:134:pipe B]
<7> [219.963023] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [219.963234] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [219.963361] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<7> [219.977904] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling DC_off
<7> [219.978020] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 02 to 00
<7> [219.983419] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CRTC:134:pipe B]
<7> [219.983508] xe 0000:00:02.0: [drm:drm_mode_setcrtc [drm]] [CONNECTOR:189:eDP-1]
<7> [220.017169] xe 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [xe]] Re-arming FIFO underruns on pipe B
<7> [220.017924] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CONNECTOR:189:eDP-1] Limiting display bpp to 30 (EDID bpp 30, max requested bpp 36, max platform bpp 36)
<7> [220.018386] xe 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [xe]] [ENCODER:188:DDI A/PHY A][CRTC:134:pipe B] DP link limits: pixel clock 347710 kHz DSC off max lanes 4 max rate 810000 max pipe_bpp 30 max link_bpp 30.0000
<7> [220.018706] xe 0000:00:02.0: [drm:intel_dp_compute_link_config [xe]] DP lane count 4 clock 432000 bpp input 30 compressed 0.0000 link rate required 1303913 available 1728000
<7> [220.019042] xe 0000:00:02.0: [drm:intel_psr_compute_config [xe]] Selective update not enabled because it would inhibit pipe CRC calculation
<7> [220.019320] xe 0000:00:02.0: [drm:intel_atomic_check [xe]] [CRTC:134:pipe B] hw max bpp: 30, pipe bpp: 30, dithering: 0
<7> [220.019642] xe 0000:00:02.0: [drm:intel_ddi_compute_config_late [xe]] [ENCODER:188:DDI A/PHY A] [CRTC:134:pipe B]
<7> [220.020097] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] [CRTC:134:pipe B] enable: yes [fastset]
<7> [220.020420] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] active: yes, output_types: EDP (0x100), output format: RGB, sink format: RGB
<7> [220.020733] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] cpu_transcoder: B, pipe bpp: 30, dithering: 0
<7> [220.021045] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] MST master transcoder: <invalid>
<7> [220.021350] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [220.021647] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] joiner: no, pipes: 0x0
<7> [220.021922] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] splitter: disabled, link count 0, overlap 0
<7> [220.022198] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dp m_n: lanes: 4; data_m: 6329869, data_n: 8388608, link_m: 421991, link_n: 524288, tu: 64
<7> [220.022475] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dp m2_n2: lanes: 4; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [220.022743] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] fec: disabled, enhanced framing: disabled
<7> [220.023017] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] sdp split: disabled
<7> [220.023269] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] psr: enabled, selective update: disabled, panel replay: disabled, selective fetch: disabled
<7> [220.023516] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] framestart delay: 1, MSA timing delay: 0
<7> [220.023749] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [220.023975] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] DP SDP: VSC, revision 2, length 8
<7> [220.024200] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pixelformat: RGB
<7> [220.024424] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] colorimetry: sRGB
<7> [220.024631] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] bpc: 0
<7> [220.024836] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dynamic range: VESA range
<7> [220.025042] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] content type: Not defined
<7> [220.025244] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] vrr: no, vmin: 1905, vmax: 2859, pipeline full: 0, guardband: 106 flipline: 1906, vmin vblank: 1800, vmax vblank: 2753
<7> [220.025438] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] requested mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906 0x48 0xa
<7> [220.025632] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] adjusted mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906 0x48 0xa
<7> [220.025827] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] crtc timings: clock=347710, hd=2880 hb=2880-3040 hs=2928-2960 ht=3040, vd=1800 vb=1800-1906 vs=1803-1809 vt=1906, flags=0xa
<7> [220.026012] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pipe mode: "2880x1800": 60 347710 2880 2928 2960 3040 1800 1803 1809 1906 0x40 0xa
<7> [220.026192] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] crtc timings: clock=347710, hd=2880 hb=2880-3040 hs=2928-2960 ht=3040, vd=1800 vb=1800-1906 vs=1803-1809 vt=1906, flags=0xa
<7> [220.026373] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] port clock: 432000, pipe src: 2880x1800+0+0, pixel rate 347710
<7> [220.026547] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] linetime: 70, ips linetime: 0
<7> [220.026714] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1, scaling_filter: 0
<7> [220.026882] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [220.027074] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] ips: 0, double wide: 0, drrs: 0
<7> [220.027096] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [220.027240] xe 0000:00:02.0: [drm:intel_crtc_state_dump [xe]] dpll_hw_state: dpll: 0x69780, dpll_md: 0x42110, fp0: 0x1a2, fp1: 0x1000000