igt@kms_psr@fbc-psr-suspend@edp-1 - incomplete - PM: suspend entry (s2idle)
<7> [844.353616] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:211:DP-MST A]
<7> [844.353650] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:212:DP-MST B]
<7> [844.353683] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:213:DP-MST C]
<7> [844.353715] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:217:DDI TC3/PHY TC3]
<7> [844.353747] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:219:DP-MST A]
<7> [844.353779] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:220:DP-MST B]
<7> [844.353810] xe 0000:00:02.0: [drm:intel_modeset_verify_disabled [xe]] [ENCODER:221:DP-MST C]
<7> [844.353843] xe 0000:00:02.0: [drm:gen9_dbuf_slices_update [xe]] Updating dbuf slices to 0xf
<7> [844.353964] xe 0000:00:02.0: [drm:intel_dbuf_mbus_join_update [xe]] Changing mbus joined: no -> yes (pipe: *)
<7> [844.354003] xe 0000:00:02.0: [drm:intel_dbuf_mdclk_cdclk_ratio_update [xe]] Updating dbuf ratio to 6 (mbus joined: yes)
<7> [844.354050] xe 0000:00:02.0: [drm:intel_power_well_enable [xe]] enabling AUX_A
<7> [844.355462] xe 0000:00:02.0: [drm:intel_pps_on_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 turn panel power on
<7> [844.355542] xe 0000:00:02.0: [drm:wait_panel_power_cycle [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 wait for panel power cycle
<7> [844.523985] xe 0000:00:02.0: [drm:wait_panel_status [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 mask: 0xb800000f value: 0x00000000 PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
<7> [844.524242] xe 0000:00:02.0: [drm:wait_panel_status [xe]] Wait complete
<7> [844.524429] xe 0000:00:02.0: [drm:intel_pps_on_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 wait for panel power on
<7> [844.524648] xe 0000:00:02.0: [drm:wait_panel_status [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 mask: 0xb000000f value: 0x80000008 PP_STATUS: 0x9000000a PP_CONTROL: 0x00000063
<7> [844.787990] xe 0000:00:02.0: [drm:wait_panel_status [xe]] Wait complete
<7> [844.790132] xe 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 turning VDD on
<7> [844.790327] xe 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [xe]] [ENCODER:188:DDI A/PHY A] PPS 0 PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
<7> [844.792348] xe 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: DPCD: 14 1e c4 c1 00 00 01 c0 02 00 02 00 08 09 84
<7> [844.793592] xe 0000:00:02.0: [drm:intel_dp_start_link_train [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Reloading eDP link rates
<7> [844.794483] xe 0000:00:02.0: [drm:intel_dp_start_link_train [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Using LINK_RATE_SET value 07
<7> [844.795439] xe 0000:00:02.0: [drm:intel_dp_set_signal_levels [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [844.796443] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Using DP training pattern TPS1
<7> [844.797678] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Clock recovery OK
<7> [844.797883] xe 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Using DP training pattern TPS4
<7> [844.830952] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Channel EQ done. DP Training successful
<7> [844.831187] xe 0000:00:02.0: [drm:intel_dp_link_train_phy [xe]] [CONNECTOR:189:eDP-1][ENCODER:188:DDI A/PHY A][DPRX] Link Training passed at link rate = 675000, lane count = 4
<7> [844.831844] xe 0000:00:02.0: [drm:intel_enable_transcoder [xe]] enabling pipe A
<7> [844.832116] xe 0000:00:02.0: [drm:intel_edp_backlight_on [xe]]
<7> [844.832298] xe 0000:00:02.0: [drm:intel_backlight_enable [xe]] pipe A
<7> [844.832485] xe 0000:00:02.0: [drm:intel_backlight_set_pwm_level [xe]] [CONNECTOR:189:eDP-1] set backlight PWM = 13892
<7> [844.833086] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] reserved 8601600 bytes of contiguous stolen space for FBC, limit: 2
<7> [844.833264] xe 0000:00:02.0: [drm:intel_fbc_update [xe]] Enabling FBC on [PLANE:32:plane 1A]
<7> [844.836402] xe 0000:00:02.0: [drm:intel_psr_post_plane_update [xe]] Enabling PSR1
<7> [844.837310] xe 0000:00:02.0: [drm:verify_connector_state [xe]] [CONNECTOR:189:eDP-1]
<7> [844.837487] xe 0000:00:02.0: [drm:intel_modeset_verify_crtc [xe]] [CRTC:82:pipe A]
<7> [844.863811] xe 0000:00:02.0: [drm:intel_power_well_disable [xe]] disabling DC_off
<7> [844.864035] xe 0000:00:02.0: [drm:skl_enable_dc6 [xe]] Enabling DC6
<7> [844.864202] xe 0000:00:02.0: [drm:gen9_set_dc_state.part.0 [xe]] Setting DC state from 00 to 02
<6> [844.979165] PM: suspend entry (s2idle)
<6> [844.979432] Filesystems sync: 0.000 seconds