mmio function fixes and improvements needed

https://lore.kernel.org/all/Y9hw0sSC58B32yPg@mdroper-desk1.amr.corp.intel.com/

diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
...
+static inline u64 xe_mmio_read64(struct xe_gt *gt, u32 reg)
+{

• if (reg < gt->mmio.adj_limit)

•       reg += gt->mmio.adj_offset;                                                                                                                                                                                                    

• return readq(gt->mmio.regs + reg);

As noted earlier, we generally don't want to be doing readq's on 64-bit
registers. There are a lot of reports of one dword coming back
properly, but the other one being all 0's or all F's. And even if both
dwords come back in the read, the read itself isn't atomic for 64-bit
registers, so trying to read a counter this way can give incorrect
results.

Also, having all of our register accesses happen on a 'gt' is kind of
ugly since a lot of the platform's register accesses are completely
unrelated to GT (i.e., sgunit, soc, display, etc.).