From 016ede332caf31d6a629d49b83c60afe538e2319 Mon Sep 17 00:00:00 2001 From: Matthew Brost <matthew.brost@intel.com> Date: Wed, 5 Apr 2023 16:20:03 -0700 Subject: [PATCH] drm/xe: Always write GEN12_RCU_MODE.GEN12_RCU_MODE_CCS_ENABLE for CCS engines If CCS0 was fused we did not write this register thus CCS engine were not enabled resulting in driver load failures. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/xe/xe_hw_engine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 63a4efd5edcc..4b56c35b988d 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -253,7 +253,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) u32 ccs_mask = xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE); - if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask & BIT(0)) + if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask) xe_mmio_write32(hwe->gt, GEN12_RCU_MODE.reg, _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); -- GitLab