igt@kms_dsc@dsc-with-bpc-formats@pipe-b-edp-1-12bpc-xrgb16161616||igt@kms_dsc@dsc-with-bpc@pipe-a-edp-1-10bpc-xrgb8888 - incomplete - No warnings/errors

https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7046/shard-tglb8/igt@kms_dsc@dsc-with-bpc-formats@pipe-b-edp-1-12bpc-xrgb16161616.html

<7> [393.462555] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:344:DDI TC3/PHY TC3]
<7> [393.462639] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:346:DP-MST A]
<7> [393.462728] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:347:DP-MST B]
<7> [393.462842] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:348:DP-MST C]
<7> [393.462977] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:349:DP-MST D]
<7> [393.463113] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:353:DDI TC4/PHY TC4]
<7> [393.463220] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:355:DP-MST A]
<7> [393.463301] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:356:DP-MST B]
<7> [393.463402] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:357:DP-MST C]
<7> [393.463486] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:358:DP-MST D]
<7> [393.463569] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] DPLL 0
<7> [393.463692] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] DPLL 1
<7> [393.463782] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TBT PLL
<7> [393.463870] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 1
<7> [393.463959] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 2
<7> [393.464047] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 3
<7> [393.464134] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 4
<7> [393.464238] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 5
<7> [393.464324] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 6
<7> [393.464413] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [393.464538] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling AUX_A
<7> [393.464634] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 0x2, on? 0) for [CRTC:167:pipe B]
<7> [393.464787] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7> [393.465008] i915 0000:00:02.0: [drm:intel_pps_on_unlocked [i915]] Turn [ENCODER:307:DDI A/PHY A] panel power on
<7> [393.465139] i915 0000:00:02.0: [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle