<7> [891.487418] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] [CRTC:80:pipe A] data rate 564000 num active planes 1
<7> [891.487504] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 0: max bw 10441 required 593
<7> [891.487590] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 1: max bw 17848 required 593
<7> [891.487676] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 2: max bw 18818 required 593
<7> [891.487760] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 3: max bw 18818 required 593
<7> [891.487856] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] PSF GV point 0: max bw 34133 required 593
<7> [891.487944] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] PSF GV point 1: max bw 51200 required 593
<7> [891.488033] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] PSF GV point 2: max bw 51200 required 593
<7> [891.488135] i915 0000:00:02.0: [drm:intel_plane_calc_min_cdclk [i915]] [PLANE:31:plane 1A] min cdclk (70500 kHz) > [CRTC:80:pipe A] min cdclk (0 kHz)
<7> [891.488225] i915 0000:00:02.0: [drm:intel_bw_calc_min_cdclk [i915]] new bandwidth min cdclk (11016 kHz) > old min cdclk (0 kHz)
<7> [891.488314] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 179200 kHz, actual 179200 kHz
<7> [891.488402] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [891.488494] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:80:pipe A] allocated DPLL 0
<7> [891.488581] i915 0000:00:02.0: [drm:icl_get_dplls [i915]] [CRTC:80:pipe A] reserving DPLL 0
<4> [891.488669] i915 0000:00:02.0: [drm] Missing PSR2 sel fetch alignment with DSC
<7> [891.488671] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:80:pipe A] enable: yes [modeset]
<7> [891.488760] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [891.488857] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] cpu_transcoder: A, pipe bpp: 30, dithering: 0
<7> [891.488943] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] MST master transcoder: <invalid>
<7> [891.489031] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [891.489110] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] bigjoiner: no, pipes: 0x0
<7> [891.489181] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] splitter: disabled, link count 0, overlap 0
<7> [891.489252] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.4 [i915]] dp m_n: lanes: 2; data_m: 2190358, data_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
<7> [891.489322] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.4 [i915]] dp m2_n2: lanes: 2; data_m: 0, data_n: 0, link_m: 0, link_n: 0, tu: 0
<7> [891.489396] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] framestart delay: 1, MSA timing delay: 0
<7> [891.489481] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [891.489566] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0