All tests - *ERROR* power well DC off state mismatch (refcount 0/enabled 1)

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10981/bat-adlp-6/igt@gem_exec_suspend@basic-s0.html#dmesg-warnings116

<7> [178.729844] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling power well A
<7> [178.729980] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling power well B
<7> [178.730066] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling power well C
<7> [178.730144] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling power well D
<7> [178.730218] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling power well 2
<7> [178.730291] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [178.730358] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<3> [178.730505] i915 0000:00:02.0: [drm] *ERROR* power well DC off state mismatch (refcount 0/enabled 1)
<7> [178.730565] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 00
<7> [178.730684] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY A already enabled, won't reprogram it.
<7> [178.730781] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY B already enabled, won't reprogram it.
<7> [178.730850] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x0
<7> [178.731158] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling power well 1
<7> [178.731328] i915 0000:00:02.0: [drm:bxt_enable_dc9 [i915]] Enabling DC9
<7> [178.731415] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 08
<6> [178.746190] ACPI: EC: interrupt blocked
<6> [194.147421] ACPI: EC: interrupt unblocked
<7> [194.276897] i915 0000:00:02.0: [drm:intel_display_power_resume_early [i915]] Resetting DC state tracking from 08 to 08
<7> [194.276991] i915 0000:00:02.0: [drm:bxt_disable_dc9 [i915]] Disabling DC9
<7> [194.277074] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 08 to 00
<7> [194.277219] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 00
<7> [194.277445] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 1
<7> [194.277766] [drm:intel_dump_cdclk_config [i915]] Current CDCLK 19200 kHz, VCO 0 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [194.277845] i915 0000:00:02.0: [drm:intel_cdclk_init_hw [i915]] Sanitizing cdclk programmed by pre-os
<7> [194.277993] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x1
<7> [194.278170] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [194.278247] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [194.278323] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 00
<7> [194.278443] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY A already enabled, won't reprogram it.
<7> [194.278543] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY B already enabled, won't reprogram it.
<7> [194.278615] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 2
<7> [194.278710] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well A
<7> [194.278798] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well B
<7> [194.278876] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well C
<7> [194.278954] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well D
<6> [194.295419] nvme nvme0: 16/0/0 default/read/poll queues
<7> [194.396032] i915 0000:00:02.0: [drm:pps_init_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
<7> [194.413028] i915 0000:00:02.0: [drm:guc_enable_communication [i915]] GuC communication enabled
<6> [194.422435] i915 0000:00:02.0: [drm] GuC firmware i915/adlp_guc_62.0.3.bin version 62.0 submission:enabled
<6> [194.422438] i915 0000:00:02.0: [drm] GuC SLPC: enabled
<6> [194.422440] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
<6> [194.422962] i915 0000:00:02.0: [drm] GuC RC: enabled