<7> [604.519735] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
<7> [604.520467] i915 0000:00:02.0: [drm:intel_bw_atomic_check [i915]] QGV point 0: max bw 17032 required 4266
<7> [604.539676] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:98:pipe A] enable: yes [fastset]
<7> [604.546036] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [604.549339] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
<7> [604.563376] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [604.566576] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [604.569453] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
<7> [604.583533] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.101 [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
<7> [604.586692] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [604.589296] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [604.589316] i915 0000:00:02.0: pixelformat: RGB
<7> [604.589335] i915 0000:00:02.0: colorimetry: sRGB
<7> [604.589353] i915 0000:00:02.0: bpc: 0
<7> [604.589372] i915 0000:00:02.0: dynamic range: VESA range
<7> [604.589399] i915 0000:00:02.0: content type: Not defined
<7> [604.589782] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [604.592351] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
<7> [604.592728] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [604.603405] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0xa
<7> [604.614704] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.102 [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0xa
<7> [604.617860] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
<7> [604.620475] [drm:drm_mode_debug_printmodeline] Modeline "3840x2160": 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x40 0xa
<7> [604.620857] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.102 [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x40 flags: 0xa
<7> [604.623938] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
<7> [604.635040] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 61, ips linetime: 0
<7> [604.640957] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [604.643971] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [604.646964] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [604.650023] i915 0000:00:02.0: [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0xe001a5, cfgcr1: 0x48, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [604.653078] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [604.656108] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [604.659147] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [NOFB], visible: no
<7> [604.670331] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:58:plane 4A] fb: [FB:368] 3840x2160 format = AR24 little-endian (0x34325241) modifier = 0x0, visible: yes
<7> [604.684367] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [604.684836] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0
<7> [604.687838] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:85:plane 7A] fb: [FB:368] 3840x2160 format = AR24 little-endian (0x34325241) modifier = 0x0, visible: yes
<7> [604.690762] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [604.701879] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0
<7> [604.715995] i915 0000:00:02.0: [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
<7> [604.737127] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [604.745656] i915 0000:00:02.0: [drm:check_phy_reg [i915]] Combo PHY A reg 001628a0 state mismatch: current 90034b5c mask e0000000 expected a0000000
<7> [604.748920] i915 0000:00:02.0: [drm:check_phy_reg [i915]] Combo PHY B reg 0006c8a0 state mismatch: current 900335dc mask e0000000 expected a0000000
<7> [604.752183] i915 0000:00:02.0: [drm:gen9_dc_off_power_well_disable [i915]] Enabling DC3CO
<7> [604.766143] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 40000000
<3> [604.772023] i915 0000:00:02.0: [drm] *ERROR* mismatch in DBUF Slices (expected 0x3, got 0x0)
<7> [604.772773] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:308:eDP-1]
<7> [604.776206] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:98:pipe A]
<7> [604.790275] i915 0000:00:02.0: [drm:intel_ddi_read_func_ctl [i915]] [ENCODER:307:DDI A/PHY A] Fec status: 0
<7> [604.793612] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.142 [i915]] DPLL 0
<7> [604.802631] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:308:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [604.816715] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz
<7> [604.819759] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [604.822711] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24
<7> [604.833754] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000
<7> [604.847858] i915 0000:00:02.0: [drm:intel_psr_compute_config [i915]] PSR2 sel fetch not enabled, disabled by parameter
<7> [604.850900] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [604.851282] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:307:DDI A/PHY A] [CRTC:98:pipe A]
<7> [604.854558] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 1983), size 0 -> 1983
<7> [604.865754] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:58:plane 4A] ddb ( 0 - 992) -> ( 0 - 0), size 992 -> 0
<7> [604.871535] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:85:plane 7A] ddb ( 992 - 1983) -> ( 0 - 0), size 991 -> 0
<7> [604.874646] i915 0000:00:02.0: [drm:gen9_disable_dc_states [i915]] Disabling DC3CO
<7> [604.877600] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm,*swm
<7> [604.878122] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 40000000 to 00