Starting dynamic subtest: eDP-1-pipe-B
(kms_flip_tiling:1529) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:453:
(kms_flip_tiling:1529) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare
Dynamic subtest eDP-1-pipe-B failed.
**** DEBUG ****
(kms_flip_tiling:1529) igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0'
(kms_flip_tiling:1529) igt_kms-DEBUG: display: eDP-1: set_pipe(B)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: eDP-1: Selecting pipe B
(kms_flip_tiling:1529) DEBUG: Test requirement passed: !(mode->flags & DRM_MODE_FLAG_INTERLACE)
(kms_flip_tiling:1529) igt_kms-DEBUG: Test requirement passed: plane_idx >= 0 && plane_idx < pipe->n_planes
(kms_flip_tiling:1529) igt_fb-DEBUG: igt_create_fb_with_bo_size(width=2400, height=1600, format=XR24(0x34325258), modifier=0x100000000000003, size=0)
(kms_flip_tiling:1529) drmtest-DEBUG: Test requirement passed: is_i915_device(fd)
(kms_flip_tiling:1529) drmtest-DEBUG: Test requirement passed: is_i915_device(fd)
(kms_flip_tiling:1529) igt_fb-DEBUG: igt_create_fb_with_bo_size(handle=1, pitch=9600)
(kms_flip_tiling:1529) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
(kms_flip_tiling:1529) igt_fb-DEBUG: igt_create_fb_with_bo_size(width=2400, height=1600, format=XR24(0x34325258), modifier=0x100000000000003, size=0)
(kms_flip_tiling:1529) drmtest-DEBUG: Test requirement passed: is_i915_device(fd)
(kms_flip_tiling:1529) drmtest-DEBUG: Test requirement passed: is_i915_device(fd)
(kms_flip_tiling:1529) igt_fb-DEBUG: igt_create_fb_with_bo_size(handle=2, pitch=9600)
(kms_flip_tiling:1529) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: plane_set_fb(130)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: plane_set_size (2400x1600)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: fb_set_position(0,0)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: fb_set_size(2400x1600)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: commit {
(kms_flip_tiling:1529) igt_kms-DEBUG: display: eDP-1: SetCrtc pipe B, fb 130, src (0, 0), mode 2400x1600
(kms_flip_tiling:1529) igt_kms-DEBUG: display: }
(kms_flip_tiling:1529) igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0'
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: plane_set_fb(129)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: plane_set_size (2400x1600)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: fb_set_position(0,0)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: B.0: fb_set_size(2400x1600)
(kms_flip_tiling:1529) igt_kms-DEBUG: display: commit {
(kms_flip_tiling:1529) igt_kms-DEBUG: display: eDP-1: SetCrtc pipe B, fb 129, src (0, 0), mode 2400x1600
(kms_flip_tiling:1529) igt_kms-DEBUG: display: }
(kms_flip_tiling:1529) DEBUG: Test requirement passed: ret == 0
(kms_flip_tiling:1529) igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0'
(kms_flip_tiling:1529) igt_debugfs-DEBUG: CRC mismatch at index 0: 0x1f69e314 != 0x4fb7c284
(kms_flip_tiling:1529) igt_debugfs-CRITICAL: Test assertion failure function igt_assert_crc_equal, file ../lib/igt_debugfs.c:453:
(kms_flip_tiling:1529) igt_debugfs-CRITICAL: Failed assertion: !mismatch || igt_skip_crc_compare
(kms_flip_tiling:1529) igt_core-INFO: Stack trace:
(kms_flip_tiling:1529) igt_core-INFO: #0 ../lib/igt_core.c:1727 __igt_fail_assert()
(kms_flip_tiling:1529) igt_core-INFO: #1 ../lib/igt_debugfs.c:454 igt_assert_crc_equal()
(kms_flip_tiling:1529) igt_core-INFO: #2 ../tests/kms_flip_tiling.c:142 test_flip_tiling.constprop.2()
(kms_flip_tiling:1529) igt_core-INFO: #3 ../tests/kms_flip_tiling.c:280 __real_main154()
(kms_flip_tiling:1529) igt_core-INFO: #4 ../tests/kms_flip_tiling.c:154 main()
(kms_flip_tiling:1529) igt_core-INFO: #5 ../csu/libc-start.c:344 __libc_start_main()
(kms_flip_tiling:1529) igt_core-INFO: #6 [_start+0x2a]
**** END ****
Dynamic subtest eDP-1-pipe-B: FAIL (3.193s)
Dmesg
<6> [873.446379] [IGT] kms_flip_tiling: starting dynamic subtest eDP-1-pipe-B
<7> [873.569075] [drm:drm_mode_addfb2] [FB:129]
<7> [873.700938] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [873.710606] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [873.716290] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [874.022968] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [874.023792] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [874.034607] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
<7> [874.057192] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<7> [874.067599] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [874.077285] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [874.078374] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [874.099131] [drm:drm_mode_addfb2] [FB:130]
<7> [874.219673] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [874.220208] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [874.235106] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
<7> [874.247341] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<7> [874.308825] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [874.309434] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [874.310561] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [874.603812] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [874.618236] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [874.618978] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
<7> [874.626168] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-on
<7> [874.748520] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [874.748958] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [874.754727] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [874.780304] [drm:drm_mode_setcrtc] [CRTC:72:pipe B]
<7> [874.780632] [drm:drm_mode_setcrtc] [CONNECTOR:95:eDP-1]
<7> [874.782201] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [874.782931] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 24 pixel clock 252750KHz
<7> [874.783839] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [874.784541] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
<7> [874.799189] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 758250 available 1080000
<7> [874.804857] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [874.805559] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:72:pipe B]
<7> [874.806324] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 2400)
<7> [874.807378] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 2560)
<7> [874.808046] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 2400)
<7> [874.808713] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 2560)
<7> [874.809283] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 2448)
<7> [874.810141] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 2480)
<7> [874.810799] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 1600)
<7> [874.811369] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 1646)
<7> [874.812019] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 1600)
<7> [874.812675] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 1646)
<7> [874.813245] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 1603)
<7> [874.814095] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 1613)
<7> [874.814773] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (2) (expected 0, found 2)
<7> [874.815299] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8)
<7> [874.820964] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 252750)
<7> [874.821749] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [CRTC:72:pipe B] dbuf slices 0x1, ddb (0 - 892), active pipes 0x2
<7> [874.822716] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] ddb ( 0 - 0) -> ( 859 - 892), size 0 -> 33
<7> [874.823624] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
<7> [874.824212] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 0, actual 0
<7> [874.824911] i915 0000:00:02.0: [drm:intel_find_shared_dpll [i915]] [CRTC:72:pipe B] allocated DPLL 0
<7> [874.825582] i915 0000:00:02.0: [drm:intel_reference_shared_dpll.isra.24 [i915]] using DPLL 0 for pipe B
<7> [874.826178] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [modeset]
<7> [874.827029] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [874.827704] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [874.828291] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [874.828976] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [874.829645] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
<7> [874.830153] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 4; gmch_m: 5889501, gmch_n: 8388608, link_m: 490791, link_n: 524288, tu: 64
<7> [874.830752] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [874.830796] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [874.830836] i915 0000:00:02.0: pixelformat: RGB
<7> [874.830876] i915 0000:00:02.0: colorimetry: sRGB
<7> [874.830997] i915 0000:00:02.0: bpc: 0
<7> [874.831038] i915 0000:00:02.0: dynamic range: VESA range
<7> [874.831073] i915 0000:00:02.0: content type: Not defined
<7> [874.831591] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [874.831650] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [874.832148] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [874.832289] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [874.832790] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x48 flags: 0xa
<7> [874.833359] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
<7> [874.833508] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x40 0xa
<7> [874.834090] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x40 flags: 0xa
<7> [874.834826] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2400x1600, pixel rate 252750
<7> [874.835413] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 82, ips linetime: 0
<7> [874.836080] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [874.836686] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [874.837190] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [874.837771] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
<7> [874.838268] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [874.838982] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [874.839656] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:130] 2400x1600 format = XR24 little-endian (0x34325258) modifier = 0x100000000000003, visible: no
<7> [874.840233] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [874.841035] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 2B] fb: [NOFB], visible: no
<7> [874.841720] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:68:cursor B] fb: [NOFB], visible: no
<7> [874.847890] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 2
<7> [874.848706] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI A/PHY A]
<7> [874.849206] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:102:DDI B/PHY B]
<7> [874.849965] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:104:DP-MST A]
<7> [874.850585] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:105:DP-MST B]
<7> [874.851089] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:106:DP-MST C]
<7> [874.851774] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:117:DDI C/PHY C]
<7> [874.852347] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:119:DP-MST A]
<7> [874.853240] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:120:DP-MST B]
<7> [874.854025] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:121:DP-MST C]
<7> [874.854704] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
<7> [874.855386] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 1
<7> [874.856119] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 2
<7> [874.856847] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 3
<7> [874.857870] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 72
<7> [874.858562] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7> [874.859419] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Turn [ENCODER:94:DDI A/PHY A] panel power on
<7> [874.860131] i915 0000:00:02.0: [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
<7> [874.860998] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
<7> [874.861910] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [874.862708] i915 0000:00:02.0: [drm:edp_panel_on [i915]] Wait for panel power on
<7> [874.863587] i915 0000:00:02.0: [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
<7> [874.924106] i915 0000:00:02.0: [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12001010, pins 0x00000010, long 0x00000010
<7> [874.924596] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:94:DDI A/PHY A] - long
<7> [874.925093] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 10
<7> [874.925869] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP [ENCODER:94:DDI A/PHY A]
<7> [875.067428] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [875.071078] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
<7> [875.079539] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD on
<7> [875.089932] i915 0000:00:02.0: [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
<7> [875.099036] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a
<7> [875.110421] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7> [875.118239] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
<7> [875.123213] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [875.128361] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
<7> [875.141500] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] clock recovery OK
<7> [875.144853] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
<7> [875.152525] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7> [875.155888] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
<7> [875.169763] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 01000000
<7> [875.178818] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7> [875.182204] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 2
<7> [875.195974] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 02000000
<7> [875.205496] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7> [875.208885] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
<7> [875.213956] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [875.227637] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] Channel EQ done. DP Training successful
<7> [875.231130] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:95:eDP-1] Link Training passed at link rate = 270000, lane count = 4, at DPRX
<7> [875.240355] i915 0000:00:02.0: [drm:intel_enable_pipe [i915]] enabling pipe B
<7> [875.252517] i915 0000:00:02.0: [drm:intel_edp_backlight_on [i915]]
<7> [875.257644] i915 0000:00:02.0: [drm:intel_panel_enable_backlight [i915]] pipe B
<7> [875.267587] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 187
<7> [875.268549] i915 0000:00:02.0: [drm:intel_psr_enable_locked [i915]] Enabling PSR1
<7> [875.282817] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [875.283838] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B]
<7> [875.285533] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
<7> [875.288722] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [875.291182] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [875.291895] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 24 pixel clock 252750KHz
<7> [875.292646] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [875.293240] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
<7> [875.294124] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 758250 available 1080000
<7> [875.294978] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [875.295796] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:72:pipe B]
<7> [875.302218] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [fastset]
<7> [875.303057] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [875.303841] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [875.304621] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [875.305284] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [875.306083] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
<7> [875.306839] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 4; gmch_m: 5889501, gmch_n: 8388608, link_m: 490791, link_n: 524288, tu: 64
<7> [875.307585] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [875.307707] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [875.307746] i915 0000:00:02.0: pixelformat: RGB
<7> [875.307782] i915 0000:00:02.0: colorimetry: sRGB
<7> [875.308037] i915 0000:00:02.0: bpc: 0
<7> [875.308078] i915 0000:00:02.0: dynamic range: VESA range
<7> [875.308189] i915 0000:00:02.0: content type: Not defined
<7> [875.308774] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [875.309005] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.309587] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [875.309717] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.310306] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x48 flags: 0xa
<7> [875.311092] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
<7> [875.311307] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x40 0xa
<7> [875.311896] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x40 flags: 0xa
<7> [875.312643] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2400x1600, pixel rate 252750
<7> [875.313293] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 82, ips linetime: 0
<7> [875.314103] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [875.314857] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [875.315602] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [875.316268] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
<7> [875.317059] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [875.317808] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [875.318570] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:130] 2400x1600 format = XR24 little-endian (0x34325258) modifier = 0x100000000000003, visible: no
<7> [875.319225] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [875.333059] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [875.334769] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B]
<7> [875.339041] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
<7> [875.384919] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [875.388303] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 24 pixel clock 252750KHz
<7> [875.402161] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [875.414961] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
<7> [875.418289] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 758250 available 1080000
<7> [875.432107] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [875.444967] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:72:pipe B]
<7> [875.452836] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [fastset]
<7> [875.462198] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [875.467217] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [875.481259] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [875.486258] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [875.499368] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
<7> [875.502656] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 4; gmch_m: 5889501, gmch_n: 8388608, link_m: 490791, link_n: 524288, tu: 64
<7> [875.506150] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [875.510667] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [875.510709] i915 0000:00:02.0: pixelformat: RGB
<7> [875.510746] i915 0000:00:02.0: colorimetry: sRGB
<7> [875.510782] i915 0000:00:02.0: bpc: 0
<7> [875.510819] i915 0000:00:02.0: dynamic range: VESA range
<7> [875.510855] i915 0000:00:02.0: content type: Not defined
<7> [875.511518] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [875.516048] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.516635] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [875.530299] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.530983] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x48 flags: 0xa
<7> [875.536124] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
<7> [875.547486] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x40 0xa
<7> [875.548225] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x40 flags: 0xa
<7> [875.553308] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2400x1600, pixel rate 252750
<7> [875.558340] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 82, ips linetime: 0
<7> [875.563327] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [875.576028] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [875.579316] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [875.584362] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
<7> [875.589524] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [875.594618] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [875.599942] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:130] 2400x1600 format = XR24 little-endian (0x34325258) modifier = 0x100000000000003, visible: no
<7> [875.609520] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [875.638677] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [875.646637] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B]
<7> [875.656530] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
<7> [875.666029] [drm:drm_mode_setcrtc] [CRTC:72:pipe B]
<7> [875.679806] [drm:drm_mode_setcrtc] [CONNECTOR:95:eDP-1]
<7> [875.724477] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe B
<7> [875.734603] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [875.740080] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 24 pixel clock 252750KHz
<7> [875.740930] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [875.741631] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
<7> [875.742224] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 758250 available 1080000
<7> [875.742927] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [875.743606] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:72:pipe B]
<7> [875.744659] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [fastset]
<7> [875.745255] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [875.745928] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [875.746590] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [875.747168] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [875.747835] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
<7> [875.748422] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 4; gmch_m: 5889501, gmch_n: 8388608, link_m: 490791, link_n: 524288, tu: 64
<7> [875.749089] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [875.749224] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [875.749261] i915 0000:00:02.0: pixelformat: RGB
<7> [875.749297] i915 0000:00:02.0: colorimetry: sRGB
<7> [875.749333] i915 0000:00:02.0: bpc: 0
<7> [875.749369] i915 0000:00:02.0: dynamic range: VESA range
<7> [875.749405] i915 0000:00:02.0: content type: Not defined
<7> [875.749980] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [875.750131] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.750712] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [875.750773] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.751366] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x48 flags: 0xa
<7> [875.752061] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
<7> [875.752299] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x40 0xa
<7> [875.752879] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x40 flags: 0xa
<7> [875.753598] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2400x1600, pixel rate 252750
<7> [875.754189] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 82, ips linetime: 0
<7> [875.754719] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [875.755252] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [875.755925] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [875.756611] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
<7> [875.757194] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [875.758351] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [875.759373] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:130] 2400x1600 format = XR24 little-endian (0x34325258) modifier = 0x100000000000003, visible: no
<7> [875.760365] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [875.770871] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [875.771589] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B]
<7> [875.773226] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0
<7> [875.825739] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:95:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
<7> [875.833484] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 24 pixel clock 252750KHz
<7> [875.838616] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7> [875.852448] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
<7> [875.857634] i915 0000:00:02.0: [drm:intel_dp_compute_config [i915]] DP link rate required 758250 available 1080000
<7> [875.862819] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [875.863375] i915 0000:00:02.0: [drm:intel_ddi_compute_config_late [i915]] [ENCODER:94:DDI A/PHY A] [CRTC:72:pipe B]
<7> [875.877152] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [fastset]
<7> [875.882180] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB
<7> [875.895861] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
<7> [875.900811] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid>
<7> [875.912712] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port sync: master transcoder: <invalid>, slave transcoder bitmask = 0x0
<7> [875.926665] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] bigjoiner: no
<7> [875.931817] i915 0000:00:02.0: [drm:intel_dump_m_n_config.isra.102 [i915]] dp m_n: lanes: 4; gmch_m: 5889501, gmch_n: 8388608, link_m: 490791, link_n: 524288, tu: 64
<7> [875.945806] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x4
<7> [875.950239] i915 0000:00:02.0: DP SDP: VSC, revision 0, length 0
<7> [875.950270] i915 0000:00:02.0: pixelformat: RGB
<7> [875.950301] i915 0000:00:02.0: colorimetry: sRGB
<7> [875.950335] i915 0000:00:02.0: bpc: 0
<7> [875.950370] i915 0000:00:02.0: dynamic range: VESA range
<7> [875.950407] i915 0000:00:02.0: content type: Not defined
<7> [875.950932] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode:
<7> [875.955401] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.955950] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7> [875.960398] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x48 0xa
<7> [875.960950] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x48 flags: 0xa
<7> [875.974716] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pipe mode:
<7> [875.979369] [drm:drm_mode_debug_printmodeline] Modeline "2400x1600": 60 252750 2400 2448 2480 2560 1600 1603 1613 1646 0x40 0xa
<7> [875.979922] i915 0000:00:02.0: [drm:intel_dump_crtc_timings.isra.103 [i915]] crtc timings: 252750 2400 2448 2480 2560 1600 1603 1613 1646, type: 0x40 flags: 0xa
<7> [875.984859] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2400x1600, pixel rate 252750
<7> [875.989810] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 82, ips linetime: 0
<7> [875.994985] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [876.008758] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [876.018691] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7> [876.028097] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
<7> [876.028724] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [876.033838] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [876.038991] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:130] 2400x1600 format = XR24 little-endian (0x34325258) modifier = 0x100000000000003, visible: no
<7> [876.052666] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1
<7> [876.083222] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [876.091196] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B]
<7> [876.099942] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.141 [i915]] DPLL 0