Skip to content

GitLab

  • Projects
  • Groups
  • Snippets
  • Help
    • Loading...
  • Help
    • Help
    • Support
    • Community forum
    • Submit feedback
    • Contribute to GitLab
  • Sign in / Register
intel
intel
  • Project overview
    • Project overview
    • Details
    • Activity
  • Issues 727
    • Issues 727
    • List
    • Boards
    • Labels
    • Service Desk
    • Milestones
  • Operations
    • Operations
    • Incidents
  • Analytics
    • Analytics
    • Value Stream
  • Wiki
    • Wiki
  • Members
    • Members
  • Activity
  • Create a new issue
  • Issue Boards
Collapse sidebar
  • drm
  • intelintel
  • Issues
  • #2574

Closed
Open
Opened Oct 14, 2020 by LAKSHMINARAYANA VUDUM@l4kshmiReporter

igt@kms_async_flips@test-time-stamp - fail - Failed assertion: vbl_time < data->flip_timestamp_us && vbl_time1 > data->flip_timestamp_us, Async flip time stamp is expected to be in between 2 vblank time stamps

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_675/fi-tgl-u2/igt@kms_async_flips@test-time-stamp.html

Starting subtest: test-time-stamp
(kms_async_flips:1226) CRITICAL: Test assertion failure function test_timestamp, file ../tests/kms_async_flips.c:284:
(kms_async_flips:1226) CRITICAL: Failed assertion: vbl_time < data->flip_timestamp_us && vbl_time1 > data->flip_timestamp_us
(kms_async_flips:1226) CRITICAL: Async flip time stamp is expected to be in between 2 vblank time stamps
Subtest test-time-stamp failed.
To upload designs, you'll need to enable LFS and have an admin enable hashed storage. More information
Assignee
Assign to
None
Milestone
None
Assign milestone
Time tracking
None
Due date
None
Reference: drm/intel#2574