igt@i915_selftest@live@gt_pm - dmesg-fail - llc state not restored upon resume!, i915/intel_gt_pm_live_selftests: live_gt_resume failed with error -5

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8373/fi-icl-u2/igt@i915_selftest@live@gt_pm.html#dmesg-warnings218

<6> [470.071357] i915: Running intel_gt_pm_live_selftests/live_gt_resume
<7> [470.388090] i915 0000:00:02.0: [drm:sandybridge_pcode_read [i915]] warning: pcode (read from mbox 9) mailbox access failed for st_llc_verify [i915]: -110
<3> [470.388093] Failed to read freq table[12], range [6, 22]
<3> [470.388100] llc state not restored upon resume!
<7> [470.388177] intel_gt_set_wedged called from intel_gt_set_wedged_on_init+0x15/0x20 [i915]
<3> [470.389305] i915/intel_gt_pm_live_selftests: live_gt_resume failed with error -5
<7> [470.389392] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [470.389919] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
<7> [470.390034] i915 0000:00:02.0: [drm:check_phy_reg [i915]] Combo PHY A reg 00162120 state mismatch: current 000d0280 mask 01000000 expected 01000000
<7> [470.390158] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 2
<7> [470.390272] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 3
<7> [470.390393] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling power well 4
<7> [470.458515] i915 0000:00:02.0: [drm:i915_hdcp_component_unbind [i915]] I915 HDCP comp unbind
<4> [470.516330] i915: probe of 0000:00:02.0 failed with error -5