1. 14 Feb, 2019 1 commit
    • José Roberto de Souza's avatar
      test: Add PSR2 selective update tests · eea5cf40
      José Roberto de Souza authored
      This tests checks if hardware is able to do selective update when
      screen changes.
      PSR2 don't trigger interruptions and the 'PSR2 SU status' register
      is not kept loaded all the times, so it is necessary keep polling
      PSR status debugfs until those values are loaded.
      
      Also from DEEP_SLEEP state HW will not do a seletive update, as
      most of the memory/context is lost in deep sleep state hardware will
      need to exit PSR mode then wait a configured number of frames to
      activate PSR again to then start doing seletive updates, that is why
      just one screen change is not enough to pass this tests.
      
      When a selective update happens and the values are loaded and read
      from debugfs it is compared with the expected value of seletive
      update blocks, if matches the polling is stopped and the test passed
      otherwise it will wait until it reachs a maximum number o screen
      changes to fail the test.
      
      v2: Using new SU blocks debugfs output
      
      v3:
      - removed the timerfd to fail the test, now failing based in a
      maximum number of screen changes
      - removing thread to read debugfs, read from main thread is enough
      - improved commit message
      
      v4:
      - getting cairo context for frontbuffer test in prepare()
      - droppoing poll(), using blocking timerfd instead
      
      v5:
      - Doing a modeset before trying to enable PSR2
      
      v6:
      - doing atomic commits to fix(legacy commit is taking more time in
      recent kernels causing us to miss the SU when reading debugfs) and
      speedup test
      - fixed code to skip test when PSR2 is not possile
      Reviewed-by: Dhinakaran Pandiyan's avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Tested-by: Dhinakaran Pandiyan's avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Signed-off-by: José Roberto de Souza's avatarJosé Roberto de Souza <jose.souza@intel.com>
      eea5cf40
  2. 01 Feb, 2019 2 commits
  3. 22 Jan, 2019 5 commits
  4. 14 Jan, 2019 2 commits
  5. 28 Sep, 2018 2 commits
  6. 20 Sep, 2018 1 commit
  7. 06 Sep, 2018 1 commit
  8. 30 Aug, 2018 1 commit
    • Maarten Lankhorst's avatar
      lib/psr: Add support for toggling edp psr through debugfs, v5. · 8f89a00c
      Maarten Lankhorst authored
      It's harmful to write to enable_psr at runtime, and the patch that allows
      us to change i915_edp_psr_debug with the panel running will require us
      to abandon the module parameter. Hence the userspace change needs to be
      put in IGT first before we can change it at kernel time.
      
      Toggling it to debugfs will mean we can skip a modeset when changing our
      feature set.
      
      Changes since v1:
      - Rebase with the previous patches dropped.
      Changes since v2:
      - Rebase on top of new api in i915_edp_psr_debug.
      Changes since v3:
      - Enable IRQ debugging for extra logging.
      - Force PSR1 mode. (dhnkrn)
      - Move PSR enable/disable functions to lib/igt_psr. (dhnkrn)
      Changes since v4:
      - Redisable irqs right away when debugfs api doesn't work. (dhnkrn)
      - Use hex everywhere. (dhnkrn)
      Signed-off-by: 's avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      [mlankhorst: Fix -ENODEV explanation in has_psr_debugfs (dhnkrn)]
      Reviewed-by: Dhinakaran Pandiyan's avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      8f89a00c
  9. 17 Jul, 2018 1 commit
  10. 05 Mar, 2018 1 commit
    • Chris Wilson's avatar
      tests/perf_pmu: Handle CPU hotplug failures better · ec872b7d
      Chris Wilson authored
      CPU hotplug, especially CPU0, can be flaky on commodity hardware.
      
      To improve test reliability and reponse times when testing larger runs we
      need to handle those cases better.
      
      Handle failures to off-line a CPU by immediately skipping the test, and
      failures to on-line a CPU by immediately rebooting the machine.
      
      This patch includes igt_sysrq_reboot implementation from Chris Wilson.
      
      v2: Halt by default, reboot if env variable IGT_REBOOT_ON_FATAL_ERROR is
          set. (Petri Latvala)
      
      v3: Add missign docs and update stale comment. (Petri Latvala)
      
      v4: Use pause instead of sleep. (Chris Wilson)
      v5: Newlines! (Chris Wilson)
      Signed-off-by: Tvrtko Ursulin's avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Petri Latvala <petri.latvala@intel.com>
      Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
      Reviewed-by: Petri Latvala's avatarPetri Latvala <petri.latvala@intel.com>
      ec872b7d
  11. 20 Aug, 2013 1 commit
  12. 17 Aug, 2013 1 commit