Commit f9a50de3 authored by Chris Wilson's avatar Chris Wilson

Introduce intel-gpu-overlay

A realtime display of GPU activity. Note, this is just at the point of
minimum usability...
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
parent 7df9caee
......@@ -21,7 +21,7 @@
ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS} -I m4
SUBDIRS = lib man tools scripts benchmarks demos
SUBDIRS = lib man tools scripts benchmarks demos overlay
if BUILD_ASSEMBLER
SUBDIRS += assembler
......
......@@ -72,6 +72,9 @@ AC_SUBST(ASSEMBLER_WARN_CFLAGS)
PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.45 libdrm])
PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
PKG_CHECK_MODULES(OVERLAY, [xv x11 xext], enable_overlay=yes, enable_overlay=no)
AM_CONDITIONAL(BUILD_OVERLAY, [test "x$enable_overlay" = xyes])
# for testdisplay
PKG_CHECK_MODULES(CAIRO, [cairo >= 1.12.0])
......@@ -184,6 +187,7 @@ AC_CONFIG_FILES([
assembler/doc/Makefile
assembler/test/Makefile
assembler/intel-gen4asm.pc
overlay/Makefile
])
AC_OUTPUT
......@@ -200,6 +204,7 @@ echo " • Tools:"
echo " Assembler : ${enable_assembler}"
echo " Debugger : ${enable_debugger}"
echo " Python dumper : ${DUMPER}"
echo " Overlay : ${enable_overlay}"
echo ""
# vim: set ft=config ts=8 sw=8 tw=0 noet :
intel-gpu-overlay
if BUILD_OVERLAY
bin_PROGRAMS = intel-gpu-overlay
endif
AM_CPPFLAGS = -I.
AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(OVERLAY_CFLAGS)
LDADD = $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(OVERLAY_LIBS)
intel_gpu_overlay_SOURCES = \
i915_pciids.h \
overlay.h \
overlay.c \
chart.h \
chart.c \
gem-objects.h \
gem-objects.c \
gpu-top.h \
gpu-top.c \
igfx.h \
igfx.c \
x11/dri2.c \
x11/dri2.h \
x11/rgb2yuv.c \
x11/rgb2yuv.h \
x11/x11-overlay.c \
$(NULL)
EXTRA_DIST=README
This is a simple overlay showing current GPU activity. An asynchronous
overlay is used, rendered by the CPU to avoid introducing any extra work
on the GPU that we wish to monitor.
The x11-overlay backend requires xf86-video-intel 2.21.15 or later, with
SNA enabled.
As it requires access to debug information, it needs to be run as root.
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <cairo.h>
#include <stdio.h>
#include "chart.h"
int chart_init(struct chart *chart, const char *name, int num_samples)
{
memset(chart, 0, sizeof(*chart));
chart->name = name;
chart->samples = malloc(sizeof(*chart->samples)*num_samples);
if (chart->samples == NULL)
return ENOMEM;
chart->num_samples = num_samples;
chart->range_automatic = 1;
return 0;
}
void chart_set_rgba(struct chart *chart, float red, float green, float blue, float alpha)
{
chart->rgb[0] = red;
chart->rgb[1] = green;
chart->rgb[2] = blue;
chart->rgb[3] = alpha;
}
void chart_set_position(struct chart *chart, int x, int y)
{
chart->x = x;
chart->y = y;
}
void chart_set_size(struct chart *chart, int w, int h)
{
chart->w = w;
chart->h = h;
}
void chart_set_range(struct chart *chart, double min, double max)
{
chart->range[0] = min;
chart->range[1] = max;
chart->range_automatic = 0;
}
void chart_add_sample(struct chart *chart, double value)
{
int pos;
pos = chart->current_sample % chart->num_samples;
chart->samples[pos] = value;
chart->current_sample++;
}
static void chart_update_range(struct chart *chart)
{
int n, max = chart->current_sample;
if (max > chart->num_samples)
max = chart->num_samples;
chart->range[0] = chart->range[1] = chart->samples[0];
for (n = 1; n < max; n++) {
if (chart->samples[n] < chart->range[0])
chart->range[0] = chart->samples[n];
else if (chart->samples[n] > chart->range[1])
chart->range[1] = chart->samples[n];
}
}
static double value_at(struct chart *chart, int n)
{
if (n <= chart->current_sample - chart->num_samples)
n = chart->current_sample;
else if (n >= chart->current_sample)
n = chart->current_sample - 1;
return chart->samples[n % chart->num_samples];
}
static double gradient_at(struct chart *chart, int n)
{
double y0, y1;
y0 = value_at(chart, n-1);
y1 = value_at(chart, n+1);
return (y1 - y0) / 2.;
}
void chart_draw(struct chart *chart, cairo_t *cr)
{
int i, n, max, x;
if (chart->current_sample == 0)
return;
if (chart->range_automatic)
chart_update_range(chart);
cairo_save(cr);
cairo_translate(cr, chart->x, chart->y + chart->h);
cairo_scale(cr,
chart->w / (double)chart->num_samples,
-chart->h / (chart->range[1] - chart->range[0]));
x = 0;
max = chart->current_sample;
if (max >= chart->num_samples) {
max = chart->num_samples;
i = chart->current_sample - max;
} else {
i = 0;
x = chart->num_samples - max;
}
cairo_translate(cr, x, -chart->range[0]);
cairo_new_path(cr);
for (n = 0; n < max; n++) {
cairo_curve_to(cr,
n-2/3., value_at(chart, i + n -1) + gradient_at(chart, i + n - 1)/3.,
n-1/3., value_at(chart, i + n) - gradient_at(chart, i + n)/3.,
n, value_at(chart, i + n));
}
cairo_identity_matrix(cr);
cairo_set_line_width(cr, 1);
cairo_set_source_rgba(cr, chart->rgb[0], chart->rgb[1], chart->rgb[2], chart->rgb[3]);
cairo_stroke(cr);
cairo_restore(cr);
}
struct chart {
const char *name;
int x, y, w, h;
int num_samples;
int current_sample;
int range_automatic;
float rgb[4];
double range[2];
double *samples;
};
int chart_init(struct chart *chart, const char *name, int num_samples);
void chart_set_rgba(struct chart *chart, float red, float green, float blue, float alpha);
void chart_set_position(struct chart *chart, int x, int y);
void chart_set_size(struct chart *chart, int w, int h);
void chart_set_range(struct chart *chart, double min, double max);
void chart_add_sample(struct chart *chart, double value);
void chart_draw(struct chart *chart, cairo_t *cr);
#include <unistd.h>
#include <fcntl.h>
#include "gem-objects.h"
int gem_objects_update(char *buf, int buflen)
{
int fd, len = -1;
fd = open("/sys/kernel/debug/dri/0/i915_gem_objects", 0);
if (fd >= 0) {
len = read(fd, buf, buflen-1);
if (len >= 0)
buf[len] = '\0';
close(fd);
}
return len;
}
int gem_objects_update(char *buf, int buflen);
#include <stdint.h>
#include <unistd.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include "igfx.h"
#include "gpu-top.h"
#define RING_TAIL 0x00
#define RING_HEAD 0x04
#define ADDR_MASK 0x001FFFFC
#define RING_CTL 0x0C
#define RING_WAIT (1<<11)
#define RING_WAIT_SEMAPHORE (1<<10)
struct ring {
int id;
uint32_t mmio;
int idle, wait, sema;
};
static void *mmio;
static uint32_t ring_read(struct ring *ring, uint32_t reg)
{
return igfx_read(mmio, ring->mmio + reg);
}
static void ring_init(struct ring *ring)
{
uint32_t ctl;
ctl = ring_read(ring, RING_CTL);
if ((ctl & 1) == 0)
ring->id = -1;
}
static void ring_reset(struct ring *ring)
{
ring->idle = 0;
ring->wait = 0;
ring->sema = 0;
}
static void ring_sample(struct ring *ring)
{
uint32_t head, tail, ctl;
if (ring->id == -1)
return;
head = ring_read(ring, RING_HEAD) & ADDR_MASK;
tail = ring_read(ring, RING_TAIL) & ADDR_MASK;
ring->idle += head == tail;
ctl = ring_read(ring, RING_CTL);
ring->wait += !!(ctl & RING_WAIT);
ring->sema += !!(ctl & RING_WAIT_SEMAPHORE);
}
static void ring_emit(struct ring *ring, int samples, union gpu_top_payload *payload)
{
if (ring->id == -1)
return;
payload[ring->id].u.busy = 100 - 100 * ring->idle / samples;
payload[ring->id].u.wait = 100 * ring->wait / samples;
payload[ring->id].u.sema = 100 * ring->sema / samples;
}
void gpu_top_init(struct gpu_top *gt)
{
struct ring render_ring = {
.mmio = 0x2030,
.id = 0,
}, bsd_ring = {
.mmio = 0x4030,
.id = 1,
}, bsd6_ring = {
.mmio = 0x12030,
.id = 1,
}, blt_ring = {
.mmio = 0x22030,
.id = 2,
};
const struct igfx_info *info;
struct pci_device *igfx;
int fd[2], i;
memset(gt, 0, sizeof(*gt));
gt->fd = -1;
igfx = igfx_get();
if (!igfx)
return;
if (pipe(fd) < 0)
return;
info = igfx_get_info(igfx);
switch (fork()) {
case -1: return;
default:
fcntl(fd[0], F_SETFL, fcntl(fd[0], F_GETFL) | O_NONBLOCK);
gt->fd = fd[0];
gt->ring[0].name = "render";
gt->num_rings = 1;
if (info->gen >= 040) {
gt->ring[1].name = "bitstream";
gt->num_rings++;
}
if (info->gen >= 060) {
gt->ring[2].name = "blt";
gt->num_rings++;
}
close(fd[1]);
return;
case 0:
close(fd[0]);
break;
}
mmio = igfx_get_mmio(igfx);
ring_init(&render_ring);
if (info->gen >= 060) {
ring_init(&bsd6_ring);
ring_init(&blt_ring);
} else if (info->gen >= 040) {
ring_init(&bsd_ring);
}
for (;;) {
union gpu_top_payload payload[MAX_RINGS];
ring_reset(&render_ring);
ring_reset(&bsd_ring);
ring_reset(&bsd6_ring);
ring_reset(&blt_ring);
for (i = 0; i < 1000; i++) {
ring_sample(&render_ring);
ring_sample(&bsd_ring);
ring_sample(&bsd6_ring);
ring_sample(&blt_ring);
usleep(1000);
}
ring_emit(&render_ring, 1000, payload);
ring_emit(&bsd_ring, 1000, payload);
ring_emit(&bsd6_ring, 1000, payload);
ring_emit(&blt_ring, 1000, payload);
write(fd[1], payload, sizeof(payload));
}
}
int gpu_top_update(struct gpu_top *gt)
{
uint32_t data[1024];
int len, update = 0;
if (gt->fd < 0)
return update;
while ((len = read(gt->fd, data, sizeof(data))) > 0) {
uint32_t *ptr = &data[len/sizeof(uint32_t) - MAX_RINGS];
gt->ring[0].u.payload = ptr[0];
gt->ring[1].u.payload = ptr[1];
gt->ring[2].u.payload = ptr[2];
gt->ring[3].u.payload = ptr[3];
update = 1;
}
return update;
}
#define MAX_RINGS 4
#include <stdint.h>
struct gpu_top {
int fd;
int num_rings;
struct gpu_top_ring {
const char *name;
union gpu_top_payload {
struct {
uint8_t busy;
uint8_t wait;
uint8_t sema;
} u;
uint32_t payload;
} u;
} ring[MAX_RINGS];
};
void gpu_top_init(struct gpu_top *gt);
int gpu_top_update(struct gpu_top *gt);
/*
* Copyright 2013 Intel Corporation
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _I915_PCIIDS_H
#define _I915_PCIIDS_H
/*
* A pci_device_id struct {
* __u32 vendor, device;
* __u32 subvendor, subdevice;
* __u32 class, class_mask;
* kernel_ulong_t driver_data;
* };
* Don't use C99 here because "class" is reserved and we want to
* give userspace flexibility.
*/
#define INTEL_VGA_DEVICE(id, info) { \
0x8086, id, \
~0, ~0, \
0x030000, 0xff0000, \
(unsigned long) info }
#define INTEL_QUANTA_VGA_DEVICE(info) { \
0x8086, 0x16a, \
0x152d, 0x8990, \
0x030000, 0xff0000, \
(unsigned long) info }
#define INTEL_I830_IDS(info) \
INTEL_VGA_DEVICE(0x3577, info)
#define INTEL_I845G_IDS(info) \
INTEL_VGA_DEVICE(0x2562, info)
#define INTEL_I85X_IDS(info) \
INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
INTEL_VGA_DEVICE(0x358e, info)
#define INTEL_I865G_IDS(info) \
INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
#define INTEL_I915G_IDS(info) \
INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
#define INTEL_I915GM_IDS(info) \
INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
#define INTEL_I945G_IDS(info) \
INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
#define INTEL_I945GM_IDS(info) \
INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
#define INTEL_I965G_IDS(info) \
INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
#define INTEL_G33_IDS(info) \
INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
#define INTEL_I965GM_IDS(info) \
INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
#define INTEL_GM45_IDS(info) \
INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
#define INTEL_G45_IDS(info) \
INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
#define INTEL_PINEVIEW_IDS(info) \
INTEL_VGA_DEVICE(0xa001, info), \
INTEL_VGA_DEVICE(0xa011, info)
#define INTEL_IRONLAKE_D_IDS(info) \
INTEL_VGA_DEVICE(0x0042, info)
#define INTEL_IRONLAKE_M_IDS(info) \
INTEL_VGA_DEVICE(0x0046, info)
#define INTEL_SNB_D_IDS(info) \
INTEL_VGA_DEVICE(0x0102, info), \
INTEL_VGA_DEVICE(0x0112, info), \
INTEL_VGA_DEVICE(0x0122, info), \
INTEL_VGA_DEVICE(0x010A, info)
#define INTEL_SNB_M_IDS(info) \
INTEL_VGA_DEVICE(0x0106, info), \
INTEL_VGA_DEVICE(0x0116, info), \
INTEL_VGA_DEVICE(0x0126, info)
#define INTEL_IVB_M_IDS(info) \
INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
#define INTEL_IVB_D_IDS(info) \
INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
#define INTEL_IVB_Q_IDS(info) \
INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
#define INTEL_HSW_D_IDS(info) \
INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
#define INTEL_HSW_M_IDS(info) \
INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
#define INTEL_VLV_M_IDS(info) \
INTEL_VGA_DEVICE(0x0f30, info), \
INTEL_VGA_DEVICE(0x0f31, info), \
INTEL_VGA_DEVICE(0x0f32, info), \
INTEL_VGA_DEVICE(0x0f33, info), \
INTEL_VGA_DEVICE(0x0157, info)
#define INTEL_VLV_D_IDS(info) \
INTEL_VGA_DEVICE(0x0155, info)
#endif /* _I915_PCIIDS_H */
#include <pciaccess.h>
#include <sys/stat.h>
#include <unistd.h>
#include <fcntl.h>
#include <stdio.h>
#include "igfx.h"
#include "i915_pciids.h"
static const struct igfx_info generic_info = {
.gen = -1,
};
static const struct igfx_info i81x_info = {
.gen = 010,
};
static const struct igfx_info i830_info = {
.gen = 020,
};
static const struct igfx_info i845_info = {
.gen = 020,
};
static const struct igfx_info i855_info = {
.gen = 021,
};
static const struct igfx_info i865_info = {
.gen = 022,
};
static const struct igfx_info i915_info = {
.gen = 030,
};
static const struct igfx_info i945_info = {
.gen = 031,
};
static const struct igfx_info g33_info = {
.gen = 033,
};
static const struct igfx_info i965_info = {
.gen = 040,
};
static const struct igfx_info g4x_info = {
.gen = 045,
};
static const struct igfx_info ironlake_info = {
.gen = 050,
};
static const struct igfx_info sandybridge_info = {
.gen = 060,
};
static const struct igfx_info ivybridge_info = {
.gen = 070,
};
static const struct igfx_info valleyview_info = {
.gen = 071,
};
static const struct igfx_info haswell_info = {
.gen = 075,
};
static const struct pci_id_match match[] = {
#if 0
INTEL_VGA_DEVICE(PCI_CHIP_I810, &i81x_info),
INTEL_VGA_DEVICE(PCI_CHIP_I810_DC100, &i81x_info),
INTEL_VGA_DEVICE(PCI_CHIP_I810_E, &i81x_info),
INTEL_VGA_DEVICE(PCI_CHIP_I815, &i81x_info),
#endif
INTEL_I830_IDS(&i830_info),
INTEL_I845G_IDS(&i830_info),
INTEL_I85X_IDS(&i855_info),