Commit c12b1f87 authored by Chris Wilson's avatar Chris Wilson

i915/gem_exec_schedule: Switch back to gem_set_domain()

The write hazard lies extend also to the cache-dirty tracking; as we
purposefully do not tell the kernel we are writing to the bo, it fails
to note the CPU cache as dirty and so the gem_read() may not
sufficiently flush the caches prior to reading back from the GPU.
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Reviewed-by: Antonio Argenziano's avatarAntonio Argenziano <antonio.argenziano@intel.com>
parent 092273f6
Pipeline #20025 passed with stages
in 9 minutes and 49 seconds
......@@ -54,7 +54,8 @@ uint32_t __sync_read_u32(int fd, uint32_t handle, uint64_t offset)
{
uint32_t value;
gem_sync(fd, handle); /* No write hazard lies! */
gem_set_domain(fd, handle, /* No write hazard lies! */
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_read(fd, handle, offset, &value, sizeof(value));
return value;
......@@ -63,7 +64,8 @@ uint32_t __sync_read_u32(int fd, uint32_t handle, uint64_t offset)
static inline
void __sync_read_u32_count(int fd, uint32_t handle, uint32_t *dst, uint64_t size)
{
gem_sync(fd, handle); /* No write hazard lies! */
gem_set_domain(fd, handle, /* No write hazard lies! */
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_read(fd, handle, 0, dst, size);
}
......
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