Commit ae539ba6 authored by Ville Syrjälä's avatar Ville Syrjälä

lib/rendercopy: Set the upper 32bits of surface base address on gen8+

gen8 introduces 48 bit virtual addresses. Set both dwords correctly
as otherwise the presumed_offset will not match what we actually
have stored in the surface state if the buffer is located somewhere
above 4GiB.

I guess we're not currently using 48bit addresses with rendercopy?
Signed-off-by: Ville Syrjälä's avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
parent 78071c2f
......@@ -155,8 +155,7 @@ struct gen8_surface_state
} ss8;
struct {
uint32_t base_addr_hi:16;
uint32_t pad0:16;
uint32_t base_addr_hi;
} ss9;
struct {
......
......@@ -172,7 +172,8 @@ gen8_bind_buf(struct intel_batchbuffer *batch,
else if (buf->tiling == I915_TILING_Y)
ss->ss0.tiled_mode = 3;
ss->ss8.base_addr = buf->bo->offset;
ss->ss8.base_addr = buf->bo->offset64;
ss->ss9.base_addr_hi = buf->bo->offset64 >> 32;
ret = drm_intel_bo_emit_reloc(batch->bo,
intel_batchbuffer_subdata_offset(batch, &ss->ss8),
......
......@@ -171,7 +171,8 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
else if (buf->tiling == I915_TILING_Y)
ss->ss0.tiled_mode = 3;
ss->ss8.base_addr = buf->bo->offset;
ss->ss8.base_addr = buf->bo->offset64;
ss->ss9.base_addr_hi = buf->bo->offset64 >> 32;
ret = drm_intel_bo_emit_reloc(batch->bo,
intel_batchbuffer_subdata_offset(batch, &ss->ss8),
......
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