Commit 7ab19ae6 authored by Jesse Barnes's avatar Jesse Barnes

intel_reg_dumper: eDP port is on the CPU, not PCH

Made me think there was another register until I checked the offset.
parent 4f12d8ac
...@@ -1566,7 +1566,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ...@@ -1566,7 +1566,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
#define ADPA_HSYNC_ACTIVE_LOW 0 #define ADPA_HSYNC_ACTIVE_LOW 0
#define PCH_eDP_A 0x64000 #define CPU_eDP_A 0x64000
#define PCH_DP_B 0xe4100 #define PCH_DP_B 0xe4100
#define PCH_DP_C 0xe4200 #define PCH_DP_C 0xe4200
#define PCH_DP_D 0xe4300 #define PCH_DP_D 0xe4300
......
...@@ -1649,7 +1649,7 @@ static struct reg_debug ironlake_debug_regs[] = { ...@@ -1649,7 +1649,7 @@ static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG2(HDMIC, ironlake_debug_hdmi), DEFINEREG2(HDMIC, ironlake_debug_hdmi),
DEFINEREG2(HDMID, ironlake_debug_hdmi), DEFINEREG2(HDMID, ironlake_debug_hdmi),
DEFINEREG2(PCH_LVDS, i830_debug_lvds), DEFINEREG2(PCH_LVDS, i830_debug_lvds),
DEFINEREG(PCH_eDP_A), DEFINEREG(CPU_eDP_A),
DEFINEREG(PCH_DP_B), DEFINEREG(PCH_DP_B),
DEFINEREG(PCH_DP_C), DEFINEREG(PCH_DP_C),
DEFINEREG(PCH_DP_D), DEFINEREG(PCH_DP_D),
......
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