Commit 7a9e536e authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Dhinakaran Pandiyan

lib/rendercopy: Add support for Yf/Ys tiling to gen9 rendercopy

Set up the surface state accordingly to support Yf/Ys tiling.

>From DK:
 Rebase.
 Move support to gen-9 surface state
Cc: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Ville Syrjälä's avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan's avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec's avatarKatarzyna Dec <katarzyna.dec@intel.com>
parent 7c2fdd9b
......@@ -67,9 +67,11 @@ struct gen9_surface_state {
struct {
uint32_t mip_count:4;
uint32_t min_lod:4;
uint32_t pad3:6;
uint32_t mip_tail_start_lod:4;
uint32_t pad3:2;
uint32_t coherency_type:1;
uint32_t pad2:5;
uint32_t pad2:3;
uint32_t trmode:2;
uint32_t ewa_disable_for_cube:1;
uint32_t y_offset:3;
uint32_t pad0:1;
......
......@@ -204,9 +204,15 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
ss->ss0.horizontal_alignment = 1; /* align 4 */
if (buf->tiling == I915_TILING_X)
ss->ss0.tiled_mode = 2;
else if (buf->tiling == I915_TILING_Y)
else if (buf->tiling != I915_TILING_NONE)
ss->ss0.tiled_mode = 3;
if (buf->tiling == I915_TILING_Yf)
ss->ss5.trmode = 1;
else if (buf->tiling == I915_TILING_Ys)
ss->ss5.trmode = 2;
ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
ss->ss8.base_addr = buf->bo->offset64;
ss->ss9.base_addr_hi = buf->bo->offset64 >> 32;
......
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