Commit 71ad19eb authored by Chris Wilson's avatar Chris Wilson

lib/i915: Pretty print HW semaphores

Include whether the scheduler is using HW semaphore assistance in our
pretty debug strings, and make the caps known for requires.
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano's avatarAntonio Argenziano <antonio.argenziano@intel.com>
parent 520b6f7f
Pipeline #24395 passed with stages
in 3 minutes and 11 seconds
......@@ -99,6 +99,8 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
/* should be kept compact */
I915_ENGINE_CLASS_INVALID = -1
};
......@@ -319,6 +321,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY 0x39
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
......@@ -476,6 +479,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_PARAM_HUC_STATUS 42
......@@ -559,6 +563,8 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
__s32 param;
/*
......@@ -574,6 +580,7 @@ typedef struct drm_i915_getparam {
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
#define I915_SETPARAM_NUM_USED_FENCES 4
/* Must be kept compact -- no holes */
typedef struct drm_i915_setparam {
int param;
......@@ -972,7 +979,7 @@ struct drm_i915_gem_execbuffer2 {
* struct drm_i915_gem_exec_fence *fences.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (7<<0)
#define I915_EXEC_RING_MASK (0x3f)
#define I915_EXEC_DEFAULT (0<<0)
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
......@@ -1120,32 +1127,34 @@ struct drm_i915_gem_busy {
* as busy may become idle before the ioctl is completed.
*
* Furthermore, if the object is busy, which engine is busy is only
* provided as a guide. There are race conditions which prevent the
* report of which engines are busy from being always accurate.
* However, the converse is not true. If the object is idle, the
* result of the ioctl, that all engines are idle, is accurate.
* provided as a guide and only indirectly by reporting its class
* (there may be more than one engine in each class). There are race
* conditions which prevent the report of which engines are busy from
* being always accurate. However, the converse is not true. If the
* object is idle, the result of the ioctl, that all engines are idle,
* is accurate.
*
* The returned dword is split into two fields to indicate both
* the engines on which the object is being read, and the
* engine on which it is currently being written (if any).
* the engine classess on which the object is being read, and the
* engine class on which it is currently being written (if any).
*
* The low word (bits 0:15) indicate if the object is being written
* to by any engine (there can only be one, as the GEM implicit
* synchronisation rules force writes to be serialised). Only the
* engine for the last write is reported.
* engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
* 1 not 0 etc) for the last write is reported.
*
* The high word (bits 16:31) are a bitmask of which engines are
* currently reading from the object. Multiple engines may be
* The high word (bits 16:31) are a bitmask of which engines classes
* are currently reading from the object. Multiple engines may be
* reading from the object simultaneously.
*
* The value of each engine is the same as specified in the
* EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
* Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
* the I915_EXEC_RENDER engine for execution, and so it is never
* The value of each engine class is the same as specified in the
* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
* reported as active itself. Some hardware may have parallel
* execution engines, e.g. multiple media engines, which are
* mapped to the same identifier in the EXECBUFFER2 ioctl and
* so are not separately reported for busyness.
* mapped to the same class identifier and so are not separately
* reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
......@@ -1511,6 +1520,7 @@ struct drm_i915_gem_context_param {
* On creation, all new contexts are marked as recoverable.
*/
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
/* Must be kept compact -- no holes and well documented */
__u64 value;
};
......@@ -1734,6 +1744,7 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
/* Must be kept compact -- no holes and well documented */
/*
* When set to zero by userspace, this is filled with the size of the
......
......@@ -67,7 +67,7 @@ unsigned gem_scheduler_capability(int fd)
}
/**
* gem_has_scheduler:
* gem_scheduler_enabled:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver has scheduling capability.
......@@ -75,11 +75,11 @@ unsigned gem_scheduler_capability(int fd)
bool gem_scheduler_enabled(int fd)
{
return gem_scheduler_capability(fd) &
LOCAL_I915_SCHEDULER_CAP_ENABLED;
I915_SCHEDULER_CAP_ENABLED;
}
/**
* gem_has_ctx_priority:
* gem_scheduler_has_ctx_priority:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports assigning custom
......@@ -88,11 +88,11 @@ bool gem_scheduler_enabled(int fd)
bool gem_scheduler_has_ctx_priority(int fd)
{
return gem_scheduler_capability(fd) &
LOCAL_I915_SCHEDULER_CAP_PRIORITY;
I915_SCHEDULER_CAP_PRIORITY;
}
/**
* gem_has_preemption:
* gem_scheduler_has_preemption:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports preempting active
......@@ -101,7 +101,21 @@ bool gem_scheduler_has_ctx_priority(int fd)
bool gem_scheduler_has_preemption(int fd)
{
return gem_scheduler_capability(fd) &
LOCAL_I915_SCHEDULER_CAP_PREEMPTION;
I915_SCHEDULER_CAP_PREEMPTION;
}
/**
* gem_scheduler_has_semaphores:
* @fd: open i915 drm file descriptor
*
* Feature test macro to query whether the driver supports using HW semaphores
* to schedule dependencies in parallel (using the HW to delay execution until
* ready to reduce latency).
*/
bool gem_scheduler_has_semaphores(int fd)
{
return gem_scheduler_capability(fd) &
I915_SCHEDULER_CAP_SEMAPHORES;
}
/**
......@@ -118,8 +132,10 @@ void gem_scheduler_print_capability(int fd)
return;
igt_info("Has kernel scheduler\n");
if (caps & LOCAL_I915_SCHEDULER_CAP_PRIORITY)
if (caps & I915_SCHEDULER_CAP_PRIORITY)
igt_info(" - With priority sorting\n");
if (caps & LOCAL_I915_SCHEDULER_CAP_PREEMPTION)
if (caps & I915_SCHEDULER_CAP_PREEMPTION)
igt_info(" - With preemption enabled\n");
if (caps & I915_SCHEDULER_CAP_SEMAPHORES)
igt_info(" - With HW semaphores enabled\n");
}
......@@ -24,14 +24,13 @@
#ifndef GEM_SCHEDULER_H
#define GEM_SCHEDULER_H
#define LOCAL_I915_SCHEDULER_CAP_ENABLED (1 << 0)
#define LOCAL_I915_SCHEDULER_CAP_PRIORITY (1 << 1)
#define LOCAL_I915_SCHEDULER_CAP_PREEMPTION (1 << 2)
#include <stdbool.h>
unsigned gem_scheduler_capability(int fd);
bool gem_scheduler_enabled(int fd);
bool gem_scheduler_has_ctx_priority(int fd);
bool gem_scheduler_has_preemption(int fd);
bool gem_scheduler_has_semaphores(int fd);
void gem_scheduler_print_capability(int fd);
#endif /* GEM_SCHEDULER_H */
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