Commit 4d0d81a2 authored by Daniel Vetter's avatar Daniel Vetter

lib/crc: Reset fifo underrun reporting for every crc capture

We have tons of issues with crc mismatches, but often by that time
there was already a fifo underrun, which disables further fifo
underrun reporting. Reset fifo underrun reporting before we capture a
crc so that it's easier to figure out why the crc mismatch happened.
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter's avatarDaniel Vetter <daniel.vetter@intel.com>
parent 54e0e8b1
......@@ -808,6 +808,8 @@ void igt_pipe_crc_start(igt_pipe_crc_t *pipe_crc)
/* Stop first just to make sure we don't have lingering state left. */
igt_pipe_crc_stop(pipe_crc);
igt_reset_fifo_underrun_reporting(pipe_crc->fd);
igt_assert_eq(write(pipe_crc->ctl_fd, src, strlen(src)), strlen(src));
sprintf(buf, "crtc-%d/crc/data", pipe_crc->pipe);
......@@ -1002,6 +1004,25 @@ void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc)
igt_pipe_crc_stop(pipe_crc);
}
/**
* igt_reset_fifo_underrun_reporting:
* @drm_fd: drm device file descriptor
*
* Resets fifo underrun reporting, if supported by the device. Useful since fifo
* underrun reporting tends to be one-shot, so good to reset it before the
* actual functional test again in case there's been a separate issue happening
* while preparing the test setup.
*/
void igt_reset_fifo_underrun_reporting(int drm_fd)
{
int fd = igt_debugfs_open(drm_fd, "i915_fifo_underrun_reset", O_WRONLY);
if (fd >= 0) {
igt_assert_eq(write(fd, "y", 1), 1);
close(fd);
}
}
/*
* Drop caches
*/
......
......@@ -216,6 +216,8 @@ void igt_require_hpd_storm_ctl(int fd);
DROP_FREED | \
DROP_IDLE)
void igt_reset_fifo_underrun_reporting(int drm_fd);
bool igt_drop_caches_has(int fd, uint64_t val);
void igt_drop_caches_set(int fd, uint64_t val);
......
......@@ -3269,14 +3269,10 @@ display_commit_changed(igt_display_t *display, enum igt_commit_style s)
}
if (display->first_commit) {
int fd = igt_debugfs_open(display->drm_fd, "i915_fifo_underrun_reset", O_WRONLY);
if (fd >= 0) {
igt_assert_eq(write(fd, "y", 1), 1);
close(fd);
}
igt_reset_fifo_underrun_reporting(display->drm_fd);
igt_display_drop_events(display);
display->first_commit = false;
}
}
......
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