Commit 1c058286 authored by Eric Anholt's avatar Eric Anholt

headers: Import drm-next uapi headers.

These will be used for tests that want to use a local copy of the
headers instead of depending on libdrm releases.  Taken from drm-next
d65d31388a23 ("Merge tag 'drm-misc-next-fixes-2017-11-07' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next")

See README for rules on updating these headers.
Signed-off-by: Eric Anholt's avatarEric Anholt <eric@anholt.net>
Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Petri Latvala's avatarPetri Latvala <petri.latvala@intel.com>
Acked-by: Daniel Vetter's avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Arkadiusz Hiler's avatarArkadiusz Hiler <arkadiusz.hiler@intel.com>
parent f8f6db9c
......@@ -126,6 +126,14 @@ docs/
intel-gpu-tools-sections.txt. Entirely new sections will also need to be
added to intel-gpu-tools-docs.xml in the appropriate place.
include/drm-uapi
Imported DRM uapi headers from airlied's drm-next branch.
These should be updated all together by executing "make
headers_install" from that branch of the kernel and then
copying the resulting ./usr/include/drm/*.h in and committing
with a note of which commit on airlied's branch was used to
generate them.
Requirements
------------
......
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/*
* Copyright (C) 2012 Russell King
* With inspiration from the i915 driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef DRM_ARMADA_IOCTL_H
#define DRM_ARMADA_IOCTL_H
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_ARMADA_GEM_CREATE 0x00
#define DRM_ARMADA_GEM_MMAP 0x02
#define DRM_ARMADA_GEM_PWRITE 0x03
#define ARMADA_IOCTL(dir, name, str) \
DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str)
struct drm_armada_gem_create {
__u32 handle;
__u32 size;
};
#define DRM_IOCTL_ARMADA_GEM_CREATE \
ARMADA_IOCTL(IOWR, GEM_CREATE, gem_create)
struct drm_armada_gem_mmap {
__u32 handle;
__u32 pad;
__u64 offset;
__u64 size;
__u64 addr;
};
#define DRM_IOCTL_ARMADA_GEM_MMAP \
ARMADA_IOCTL(IOWR, GEM_MMAP, gem_mmap)
struct drm_armada_gem_pwrite {
__u64 ptr;
__u32 handle;
__u32 offset;
__u32 size;
};
#define DRM_IOCTL_ARMADA_GEM_PWRITE \
ARMADA_IOCTL(IOW, GEM_PWRITE, gem_pwrite)
#if defined(__cplusplus)
}
#endif
#endif
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/**
* \file drm_sarea.h
* \brief SAREA definitions
*
* \author Michel Dänzer <michel@daenzer.net>
*/
/*
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DRM_SAREA_H_
#define _DRM_SAREA_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* SAREA area needs to be at least a page */
#if defined(__alpha__)
#define SAREA_MAX 0x2000U
#elif defined(__mips__)
#define SAREA_MAX 0x4000U
#elif defined(__ia64__)
#define SAREA_MAX 0x10000U /* 64kB */
#else
/* Intel 830M driver needs at least 8k SAREA */
#define SAREA_MAX 0x2000U
#endif
/** Maximum number of drawables in the SAREA */
#define SAREA_MAX_DRAWABLES 256
#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
/** SAREA drawable */
struct drm_sarea_drawable {
unsigned int stamp;
unsigned int flags;
};
/** SAREA frame */
struct drm_sarea_frame {
unsigned int x;
unsigned int y;
unsigned int width;
unsigned int height;
unsigned int fullscreen;
};
/** SAREA */
struct drm_sarea {
/** first thing is always the DRM locking structure */
struct drm_hw_lock lock;
/** \todo Use readers/writer lock for drm_sarea::drawable_lock */
struct drm_hw_lock drawable_lock;
struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
struct drm_sarea_frame frame; /**< frame */
drm_context_t dummy_context;
};
typedef struct drm_sarea_drawable drm_sarea_drawable_t;
typedef struct drm_sarea_frame drm_sarea_frame_t;
typedef struct drm_sarea drm_sarea_t;
#if defined(__cplusplus)
}
#endif
#endif /* _DRM_SAREA_H_ */
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/* exynos_drm.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* Authors:
* Inki Dae <inki.dae@samsung.com>
* Joonyoung Shim <jy0922.shim@samsung.com>
* Seung-Woo Kim <sw0312.kim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _EXYNOS_DRM_H_
#define _EXYNOS_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* User-desired buffer creation information structure.
*
* @size: user-desired memory allocation size.
* - this size value would be page-aligned internally.
* @flags: user request for setting memory type or cache attributes.
* @handle: returned a handle to created gem object.
* - this handle will be set by gem module of kernel side.
*/
struct drm_exynos_gem_create {
__u64 size;
__u32 flags;
__u32 handle;
};
/**
* A structure for getting a fake-offset that can be used with mmap.
*
* @handle: handle of gem object.
* @reserved: just padding to be 64-bit aligned.
* @offset: a fake-offset of gem object.
*/
struct drm_exynos_gem_map {
__u32 handle;
__u32 reserved;
__u64 offset;
};
/**
* A structure to gem information.
*
* @handle: a handle to gem object created.
* @flags: flag value including memory type and cache attribute and
* this value would be set by driver.
* @size: size to memory region allocated by gem and this size would
* be set by driver.
*/
struct drm_exynos_gem_info {
__u32 handle;
__u32 flags;
__u64 size;
};
/**
* A structure for user connection request of virtual display.
*
* @connection: indicate whether doing connetion or not by user.
* @extensions: if this value is 1 then the vidi driver would need additional
* 128bytes edid data.
* @edid: the edid data pointer from user side.
*/
struct drm_exynos_vidi_connection {
__u32 connection;
__u32 extensions;
__u64 edid;
};
/* memory type definitions. */
enum e_drm_exynos_gem_mem_type {
/* Physically Continuous memory and used as default. */
EXYNOS_BO_CONTIG = 0 << 0,
/* Physically Non-Continuous memory. */
EXYNOS_BO_NONCONTIG = 1 << 0,
/* non-cachable mapping and used as default. */
EXYNOS_BO_NONCACHABLE = 0 << 1,
/* cachable mapping. */
EXYNOS_BO_CACHABLE = 1 << 1,
/* write-combine mapping. */
EXYNOS_BO_WC = 1 << 2,
EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
EXYNOS_BO_WC
};
struct drm_exynos_g2d_get_ver {
__u32 major;
__u32 minor;
};
struct drm_exynos_g2d_cmd {
__u32 offset;
__u32 data;
};
enum drm_exynos_g2d_buf_type {
G2D_BUF_USERPTR = 1 << 31,
};
enum drm_exynos_g2d_event_type {
G2D_EVENT_NOT,
G2D_EVENT_NONSTOP,
G2D_EVENT_STOP, /* not yet */
};
struct drm_exynos_g2d_userptr {
unsigned long userptr;
unsigned long size;
};
struct drm_exynos_g2d_set_cmdlist {
__u64 cmd;
__u64 cmd_buf;
__u32 cmd_nr;
__u32 cmd_buf_nr;
/* for g2d event */
__u64 event_type;
__u64 user_data;
};
struct drm_exynos_g2d_exec {
__u64 async;
};
enum drm_exynos_ops_id {
EXYNOS_DRM_OPS_SRC,
EXYNOS_DRM_OPS_DST,
EXYNOS_DRM_OPS_MAX,
};
struct drm_exynos_sz {
__u32 hsize;
__u32 vsize;
};
struct drm_exynos_pos {
__u32 x;
__u32 y;
__u32 w;
__u32 h;
};
enum drm_exynos_flip {
EXYNOS_DRM_FLIP_NONE = (0 << 0),
EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
EXYNOS_DRM_FLIP_HORIZONTAL,
};
enum drm_exynos_degree {
EXYNOS_DRM_DEGREE_0,
EXYNOS_DRM_DEGREE_90,
EXYNOS_DRM_DEGREE_180,
EXYNOS_DRM_DEGREE_270,
};
enum drm_exynos_planer {
EXYNOS_DRM_PLANAR_Y,
EXYNOS_DRM_PLANAR_CB,
EXYNOS_DRM_PLANAR_CR,
EXYNOS_DRM_PLANAR_MAX,
};
/**
* A structure for ipp supported property list.
*
* @version: version of this structure.
* @ipp_id: id of ipp driver.
* @count: count of ipp driver.
* @writeback: flag of writeback supporting.
* @flip: flag of flip supporting.
* @degree: flag of degree information.
* @csc: flag of csc supporting.
* @crop: flag of crop supporting.
* @scale: flag of scale supporting.
* @refresh_min: min hz of refresh.
* @refresh_max: max hz of refresh.
* @crop_min: crop min resolution.
* @crop_max: crop max resolution.
* @scale_min: scale min resolution.
* @scale_max: scale max resolution.
*/
struct drm_exynos_ipp_prop_list {
__u32 version;
__u32 ipp_id;
__u32 count;
__u32 writeback;
__u32 flip;
__u32 degree;
__u32 csc;
__u32 crop;
__u32 scale;
__u32 refresh_min;
__u32 refresh_max;
__u32 reserved;
struct drm_exynos_sz crop_min;
struct drm_exynos_sz crop_max;
struct drm_exynos_sz scale_min;
struct drm_exynos_sz scale_max;
};
/**
* A structure for ipp config.
*
* @ops_id: property of operation directions.
* @flip: property of mirror, flip.
* @degree: property of rotation degree.
* @fmt: property of image format.
* @sz: property of image size.
* @pos: property of image position(src-cropped,dst-scaler).
*/
struct drm_exynos_ipp_config {
__u32 ops_id;
__u32 flip;
__u32 degree;
__u32 fmt;
struct drm_exynos_sz sz;
struct drm_exynos_pos pos;
};
enum drm_exynos_ipp_cmd {
IPP_CMD_NONE,
IPP_CMD_M2M,
IPP_CMD_WB,
IPP_CMD_OUTPUT,
IPP_CMD_MAX,
};
/**
* A structure for ipp property.
*
* @config: source, destination config.
* @cmd: definition of command.
* @ipp_id: id of ipp driver.
* @prop_id: id of property.
* @refresh_rate: refresh rate.
*/
struct drm_exynos_ipp_property {
struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
__u32 cmd;
__u32 ipp_id;
__u32 prop_id;
__u32 refresh_rate;
};
enum drm_exynos_ipp_buf_type {
IPP_BUF_ENQUEUE,
IPP_BUF_DEQUEUE,
};
/**
* A structure for ipp buffer operations.
*
* @ops_id: operation directions.
* @buf_type: definition of buffer.
* @prop_id: id of property.
* @buf_id: id of buffer.
* @handle: Y, Cb, Cr each planar handle.
* @user_data: user data.
*/
struct drm_exynos_ipp_queue_buf {
__u32 ops_id;
__u32 buf_type;
__u32 prop_id;
__u32 buf_id;
__u32 handle[EXYNOS_DRM_PLANAR_MAX];
__u32 reserved;
__u64 user_data;
};
enum drm_exynos_ipp_ctrl {
IPP_CTRL_PLAY,
IPP_CTRL_STOP,
IPP_CTRL_PAUSE,
IPP_CTRL_RESUME,
IPP_CTRL_MAX,
};
/**
* A structure for ipp start/stop operations.
*
* @prop_id: id of property.
* @ctrl: definition of control.
*/
struct drm_exynos_ipp_cmd_ctrl {
__u32 prop_id;
__u32 ctrl;
};
#define DRM_EXYNOS_GEM_CREATE 0x00
#define DRM_EXYNOS_GEM_MAP 0x01
/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
#define DRM_EXYNOS_GEM_GET 0x04
#define DRM_EXYNOS_VIDI_CONNECTION 0x07
/* G2D */
#define DRM_EXYNOS_G2D_GET_VER 0x20
#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
#define DRM_EXYNOS_G2D_EXEC 0x22
/* IPP - Image Post Processing */
#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
/* EXYNOS specific events */
#define DRM_EXYNOS_G2D_EVENT 0x80000000
#define DRM_EXYNOS_IPP_EVENT 0x80000001
struct drm_exynos_g2d_event {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 cmdlist_no;
__u32 reserved;
};
struct drm_exynos_ipp_event {
struct drm_event base;
__u64 user_data;
__u32 tv_sec;
__u32 tv_usec;
__u32 prop_id;
__u32 reserved;
__u32 buf_id[EXYNOS_DRM_OPS_MAX];
};
#if defined(__cplusplus)
}
#endif
#endif /* _EXYNOS_DRM_H_ */
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/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__
#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
#define NOUVEAU_GEM_TILE_16BPP 0x00000001
#define NOUVEAU_GEM_TILE_32BPP 0x00000002
#define NOUVEAU_GEM_TILE_ZETA 0x00000004
#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
struct drm_nouveau_gem_info {
__u32 handle;
__u32 domain;
__u64 size;
__u64 offset;
__u64 map_handle;
__u32 tile_mode;
__u32 tile_flags;
};
struct drm_nouveau_gem_new {
struct drm_nouveau_gem_info info;
__u32 channel_hint;
__u32 align;
};
#define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed {
__u32 valid;
__u32 domain;
__u64 offset;
};
struct drm_nouveau_gem_pushbuf_bo {
__u64 user_priv;
__u32 handle;
__u32 read_domains;
__u32 write_domains;
__u32 valid_domains;
struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
};
#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
#define NOUVEAU_GEM_RELOC_OR (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc {
__u32 reloc_bo_index;
__u32 reloc_bo_offset;
__u32 bo_index;
__u32 flags;
__u32 data;
__u32 vor;
__u32 tor;
};
#define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push {
__u32 bo_index;
__u32 pad;
__u64 offset;
__u64 length;
};
struct drm_nouveau_gem_pushbuf {
__u32 channel;
__u32 nr_buffers;
__u64 buffers;
__u32 nr_relocs;
__u32 nr_push;
__u64 relocs;
__u64 push;
__u32 suffix0;
__u32 suffix1;
__u64 vram_available;
__u64 gart_available;
};
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
struct drm_nouveau_gem_cpu_prep {
__u32 handle;
__u32 flags;
};
struct drm_nouveau_gem_cpu_fini {
__u32 handle;
};
#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
#define DRM_NOUVEAU_NVIF 0x07
#define DRM_NOUVEAU_GEM_NEW 0x40
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
#define DRM_NOUVEAU_GEM_INFO 0x44
#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
#if defined(__cplusplus)
}
#endif
#endif /* __NOUVEAU_DRM_H__ */
/*
* include/uapi/drm/omap_drm.h
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __OMAP_DRM_H__
#define __OMAP_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*/
#define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */
struct drm_omap_param {
__u64 param; /* in */
__u64 value; /* in (set_param), out (get_param) */
};
#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable (phys contiguous) */
#define OMAP_BO_CACHE_MASK 0x00000006 /* cache type mask, see cache modes */
#define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
/* cache modes */
#define OMAP_BO_CACHED 0x00000000 /* default */
#define OMAP_BO_WC 0x00000002 /* write-combine */
#define OMAP_BO_UNCACHED 0x00000004 /* strongly-ordered (uncached) */
/* tiled modes */