Commit 0efa6c7b authored by Daniel Vetter's avatar Daniel Vetter

tools/reg_dumper: really dump pipe C regs

Not just a copy of pipe B. Meh.

Also kill a few redudant #define for pipe B - they match pipe A.
parent 9fcaffda
......@@ -1096,6 +1096,16 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BCLRPAT_B 0x61020
#define VSYNCSHIFT_B 0x61028
#define HTOTAL_C 0x62000
#define HBLANK_C 0x62004
#define HSYNC_C 0x62008
#define VTOTAL_C 0x6200c
#define VBLANK_C 0x62010
#define VSYNC_C 0x62014
#define PIPECSRC 0x6201c
#define BCLRPAT_C 0x62020
#define VSYNCSHIFT_C 0x62028
#define PP_STATUS 0x61200
# define PP_ON (1 << 31)
/**
......@@ -2500,13 +2510,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPEB_DSL 0x71000
#define PIPEBCONF 0x71008
#define PIPEBCONF_ENABLE (1<<31)
#define PIPEBCONF_DISABLE 0
#define PIPEBCONF_DOUBLE_WIDE (1<<30)
#define PIPEBCONF_DISABLE 0
#define PIPEBCONF_GAMMA (1<<24)
#define PIPEBCONF_PALETTE 0
#define PIPEBCONF 0x71008
#define PIPEBGCMAXRED 0x71010
#define PIPEBGCMAXGREEN 0x71014
......@@ -2520,8 +2524,23 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPEB_DP_LINK_M 0x71060
#define PIPEB_DP_LINK_N 0x71064
#define PIPECCONF 0x72008
#define PIPECGCMAXRED 0x72010
#define PIPECGCMAXGREEN 0x72014
#define PIPECGCMAXBLUE 0x72018
#define PIPECSTAT 0x72024
#define PIPECFRAMEHIGH 0x72040
#define PIPECFRAMEPIXEL 0x72044
#define PIPEC_GMCH_DATA_M 0x72050
#define PIPEC_GMCH_DATA_N 0x72054
#define PIPEC_DP_LINK_M 0x72060
#define PIPEC_DP_LINK_N 0x72064
#define DSPACNTR 0x70180
#define DSPBCNTR 0x71180
#define DSPCCNTR 0x72180
#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPLAY_PLANE_TILED (1<<10)
......@@ -2557,6 +2576,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DSPBADDR DSPBBASE
#define DSPBSTRIDE 0x71188
#define DSPCBASE 0x72184
#define DSPCADDR DSPCBASE
#define DSPCSTRIDE 0x72188
#define DSPAKEYVAL 0x70194
#define DSPAKEYMASK 0x70198
......@@ -2571,6 +2594,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DSPBSURF 0x7119C
#define DSPBTILEOFF 0x711A4
#define DSPCSURF 0x7219C
#define DSPCTILEOFF 0x721A4
#define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31)
# define VGA_2X_MODE (1 << 30)
......@@ -2977,24 +3003,30 @@ typedef enum {
/* PIPEB timing regs are same start from 0x61000 */
#define PIPEB_DATA_M1 0x61030
#define PIPEB_DATA_M1_OFFSET 0
#define PIPEB_DATA_N1 0x61034
#define PIPEB_DATA_N1_OFFSET 0
#define PIPEB_DATA_M2 0x61038
#define PIPEB_DATA_M2_OFFSET 0
#define PIPEB_DATA_N2 0x6103c
#define PIPEB_DATA_N2_OFFSET 0
#define PIPEB_LINK_M1 0x61040
#define PIPEB_LINK_M1_OFFSET 0
#define PIPEB_LINK_N1 0x61044
#define PIPEB_LINK_N1_OFFSET 0
#define PIPEB_LINK_M2 0x61048
#define PIPEB_LINK_M2_OFFSET 0
#define PIPEB_LINK_N2 0x6104c
#define PIPEB_LINK_N2_OFFSET 0
/* PIPEC timing regs */
#define PIPEC_DATA_M1 0x62030
#define PIPEC_DATA_N1 0x62034
#define PIPEC_DATA_M2 0x62038
#define PIPEC_DATA_N2 0x6203c
#define PIPEC_LINK_M1 0x62040
#define PIPEC_LINK_N1 0x62044
#define PIPEC_LINK_M2 0x62048
#define PIPEC_LINK_N2 0x6204c
/* PIPECONF for pipe A/B addr is same */
......
......@@ -1646,6 +1646,37 @@ static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG(DSPBSURF),
DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
/* pipe C */
DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_C),
DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n),
DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n),
DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
DEFINEREG(DSPCBASE),
DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPCSURF),
DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
/* Panel fitter */
DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
......@@ -1665,35 +1696,6 @@ static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
/* pipe C */
DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
DEFINEREG(VSYNCSHIFT_B),
DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu),
DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n),
DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
DEFINEREG(DSPBBASE),
DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
DEFINEREG(DSPBSURF),
DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
/* PCH */
DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl),
......
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