hersen wu authored Jan 17, 2024 and Alex Hung committed Jan 26, 2024

When igt app call this debugfs, it will pass disable flag
to kernel. The flag  will block psr setup and enable.

When igt read psr edp rx crc, read may be timeout.
After bootup, AMD kernel driver setup psr with dpcd 0x170 = 5.
this notify rx psr enable and let rx fw start checking crc
for rx fw internal logic. rx fw may not update crc read count
within dpcd 0x246. read count is always 0. this  will lead tx
crc reading timeout.

With IGT app sequence below, rx fw crc checking for rx internal
logic is disabled. upon tx read rx crc, rx fw will check crc and
update crc count within dpcd 0x246. so IGT app can read rx crc
successfully.

expected app sequence is as below:
1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
   without dpcd 0x170 = 5.
4. read crc from rx dpcd 0x270, 0x246, etc.
5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/di...