Dale Stimson authored Mar 04, 2019 and Chris Wilson committed Mar 05, 2019

This patch is a change to igt file tests/i915/gem_ctx_isolation.c to
add and enable Gen11 support.

This patch accounts for whitelisted registers appropriately for the
different Gen levels.

This patch accounts for the changed MMIO offsets of Gen11.

This patch redefines MAX_REG from 0x40000 to 0x200000 due to the
larger total register space for Gen11 mmio offsets.

A current Gen11 SKU has two video engines (with indexes 0 and 2,
for VCS0 and VCS2), with VCS1 not being used.

Current kernel and igt limitations only allow for VCS0 and VCS1.
Those limitations are in the process of being removed.  See for
example the RFC/PATCH series on igt-dev from Andy Shyti:
    [igt-dev] [RFC PATCH v9 0/5] new engine discovery interface
which depends on in-process kernel "media scalability" patches.

Lacking the above infrastructure at the moment:

The array of registers to be tested includes VCS2 and VCS3 registers.
They are present as a provision for the future, but they will
not actually be tested as those engines are not yet known to the
underlying infrastructure.

When run on Gen11 this patch skips the sub-tests for the non-existent VCS1
with these warnings:
  Test requirement not met in function gem_require_engine, file ../lib/igt_gt.h:114:
  Test requirement: gem_has_engine(gem_fd, class, instance)

Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>