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Tvrtko Ursulin authored
Simulates a single decoder feeding multiple processing and encoding pipelines. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
65173e1a
Simulates a single decoder feeding multiple processing and
encoding pipelines.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>