1. 26 Sep, 2017 1 commit
    • Daniel Vetter's avatar
      meson: Simple makefile integration · 0a91a5e9
      Daniel Vetter authored
      Run ./meson.sh once, then you have
      $ make
      $ make test
      available in the normal src root.
      $ make reconfigure
      which is the meson equivalent to rerunning ./configure. Also takes
      some arguments if needed. Start out with --help, as usual.
      v3: Use ninja -C (Chris).
      v4: Catch more automake targets and point out what's happening
      v5: Use EOF as heredoc marker (Arek)
      Cc: Petri Latvala <petri.latvala@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: Arkadiusz Hiler's avatarArkadiusz Hiler <arkadiusz.hiler@intel.com>
      Signed-off-by: Daniel Vetter's avatarDaniel Vetter <daniel.vetter@ffwll.ch>
  2. 25 Sep, 2017 5 commits
  3. 22 Sep, 2017 8 commits
  4. 21 Sep, 2017 3 commits
    • Rodrigo Vivi's avatar
      i915_pciids: Change a KBL pci id to GT2 from GT1.5 · 74778b83
      Rodrigo Vivi authored
      In sync with 41693fd52373 ("drm/i915/kbl: Change a KBL pci id
      to GT2 from GT1.5")
      "See Mesa commit 9c588ff"
      v2: s/DT/Mobile
      Cc: Anuj Phogat <anuj.phogat@gmail.com>
      Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: Anuj Phogat's avatarAnuj Phogat <anuj.phogat@gmail.com>
    • Kenneth Graunke's avatar
      intel_aubdump: Support I915_EXEC_BATCH_FIRST. · 7c2650a1
      Kenneth Graunke authored
      The batch is now on the other end of the list.
      Fixes issues where modern Mesa and modern kernels together start putting
      the batch at the front of the list, and intel_aubdump looks for it at
      the end of the list, causing it to interpret some other buffer as the
      batch.  Then AubLoad or aubinator see bogus data like 1.0 float as a
      GPU command and get grumpy.
    • Chris Wilson's avatar
      igt/prime_vgem: Split out the fine-grain coherency check · f86dc17c
      Chris Wilson authored
      We don't expect every machine to be able to pass the WC/GTT coherency
      check, see
      kernel commit 3b5724d702ef24ee41ca008a1fab1cf94f3d31b5
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Thu Aug 18 17:16:49 2016 +0100
          drm/i915: Wait for writes through the GTT to land before reading back
          If we quickly switch from writing through the GTT to a read of the
          physical page directly with the CPU (e.g. performing relocations through
          the GTT and then running the command parser), we can observe that the
          writes are not visible to the CPU. It is not a coherency problem, as
          extensive investigations with clflush have demonstrated, but a mere
          timing issue - we have to wait for the GTT to complete it's write before
          we start our read from the CPU.
          The issue can be illustrated in userspace with:
                  gtt = gem_mmap__gtt(fd, handle, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
                  cpu = gem_mmap__cpu(fd, handle, 0, OBJECT_SIZE, PROT_READ | PROT_WRITE);
                  gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
                  for (i = 0; i < OBJECT_SIZE / 64; i++) {
                          int x = 16*i + (i%16);
                          gtt[x] = i;
                          clflush(&cpu[x], sizeof(cpu[x]));
                          assert(cpu[x] == i);
          Experimenting with that shows that this behaviour is indeed limited to
          recent Atom-class hardware.
      so split out the interleave coherency check from the basic
      interopability check.
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102577Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: Michał Winiarski's avatarMichał Winiarski <michal.winiarski@intel.com>
  5. 20 Sep, 2017 3 commits
  6. 19 Sep, 2017 5 commits
  7. 18 Sep, 2017 3 commits
  8. 15 Sep, 2017 12 commits