Commit ba6c4e6e authored by Chris Wilson's avatar Chris Wilson 🤔

igt/perf_pmu: Increase delay for rc6 to start

I was thinking of the RC6 threshold parameter, but needed to consider
the RC6 evaluation interval instead. RC6 doesn't enable until activity
is below the threshold inside an evaluation interval, therefore we need
to wait at least 2 EI after idling before we can expect RC6 to be
enabled.

Fixes: 55a17bc2 ("igt/perf_pmu: Reduce arbitrary delays before rc6")
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
parent 62b7723e
......@@ -985,6 +985,19 @@ test_frequency(int gem_fd)
igt_assert(min[1] < max[1]);
}
static unsigned long rc6_enable_us(void)
{
/*
* To know how long we need to wait for the device to enter rc6 once
* idle, we need to look at GEN6_RC_EVALUATION_INTERVAL. Currently,
* this is set to 125000 (12500 * 1280ns or 0.16s) on all platforms.
* We must complete at least one EI with activity below the
* per-platform threshold for RC6 to kick. Therefore, we must wait
* at least 2 EI cycles, before we can expect rc6 to start ticking.
*/
return 2 * 160 * 1000;
}
static void
test_rc6(int gem_fd)
{
......@@ -996,7 +1009,7 @@ test_rc6(int gem_fd)
fd = open_pmu(I915_PMU_RC6_RESIDENCY);
gem_quiescent_gpu(gem_fd);
usleep(100e3); /* wait for the rc6 cycle counter to kick in */
usleep(rc6_enable_us()); /* wait for the rc6 cycle counter to kick in */
/* Go idle and check full RC6. */
prev = pmu_read_single(fd);
......
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