Commit 94b866b6 authored by Antonio Argenziano's avatar Antonio Argenziano Committed by Chris Wilson

tests/i915/gem_storedw*: Remove tests

Tests have been replaced by gem_exec_store.
Signed-off-by: Antonio Argenziano's avatarAntonio Argenziano <antonio.argenziano@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
parent e820637f
......@@ -393,12 +393,6 @@ gem_spin_batch_SOURCES = i915/gem_spin_batch.c
TESTS_progs += gem_stolen
gem_stolen_SOURCES = i915/gem_stolen.c
TESTS_progs += gem_storedw_batches_loop
gem_storedw_batches_loop_SOURCES = i915/gem_storedw_batches_loop.c
TESTS_progs += gem_storedw_loop
gem_storedw_loop_SOURCES = i915/gem_storedw_loop.c
TESTS_progs += gem_streaming_writes
gem_streaming_writes_SOURCES = i915/gem_streaming_writes.c
......
/*
* Copyright © 2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
* Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
*
*/
#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
#include "drm.h"
#include "intel_bufmgr.h"
static drm_intel_bufmgr *bufmgr;
static drm_intel_bo *target_bo;
static int has_ppgtt = 0;
#define SECURE_DISPATCH (1<<0)
/* Like the store dword test, but we create new command buffers each time */
static void
store_dword_loop(int divider, unsigned flags)
{
int cmd, i, val = 0;
uint32_t *buf;
drm_intel_bo *cmd_bo;
igt_info("running storedw loop with stall every %i batch\n", divider);
cmd = MI_STORE_DWORD_IMM;
if (!has_ppgtt)
cmd |= MI_MEM_VIRTUAL;
for (i = 0; i < SLOW_QUICK(0x2000, 4); i++) {
int j = 0;
int cmd_address_offset;
cmd_bo = drm_intel_bo_alloc(bufmgr, "cmd bo", 4096, 4096);
igt_assert(cmd_bo);
/* Upload through cpu mmaps to make sure we don't have a gtt
* mapping which could paper over secure batch submission
* failing to bind that. */
drm_intel_bo_map(cmd_bo, 1);
buf = cmd_bo->virtual;
buf[j++] = cmd;
if (intel_gen(drm_intel_bufmgr_gem_get_devid(bufmgr)) >= 8) {
cmd_address_offset = j * 4;
buf[j++] = target_bo->offset;
buf[j++] = 0;
} else {
buf[j++] = 0;
cmd_address_offset = j * 4;
buf[j++] = target_bo->offset;
}
igt_assert_lt(0, j);
buf[j++] = 0x42000000 + val;
igt_assert(drm_intel_bo_references(cmd_bo, target_bo) == 0);
igt_assert(drm_intel_bo_emit_reloc(cmd_bo, cmd_address_offset, target_bo, 0,
I915_GEM_DOMAIN_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION) == 0);
buf[j++] = MI_BATCH_BUFFER_END;
buf[j++] = MI_BATCH_BUFFER_END;
drm_intel_bo_unmap(cmd_bo);
igt_assert(drm_intel_bo_references(cmd_bo, target_bo) == 1);
#define LOCAL_I915_EXEC_SECURE (1<<9)
igt_assert(drm_intel_bo_mrb_exec(cmd_bo, j * 4, NULL, 0, 0,
I915_EXEC_BLT |
(flags & SECURE_DISPATCH ? LOCAL_I915_EXEC_SECURE : 0))
== 0);
if (i % divider != 0)
goto cont;
drm_intel_bo_wait_rendering(cmd_bo);
drm_intel_bo_map(target_bo, 1);
buf = target_bo->virtual;
igt_assert_f(buf[0] == (0x42000000 | val),
"value mismatch: cur 0x%08x, stored 0x%08x\n",
buf[0], 0x42000000 | val);
buf[0] = 0; /* let batch write it again */
drm_intel_bo_unmap(target_bo);
cont:
drm_intel_bo_unreference(cmd_bo);
val++;
}
igt_info("completed %d writes successfully\n", i);
}
int fd;
int devid;
igt_main
{
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
devid = intel_get_drm_devid(fd);
has_ppgtt = gem_uses_ppgtt(fd);
/* storedw needs gtt address on gen4+/g33 and snoopable memory.
* Strictly speaking we could implement this now ... */
igt_require(intel_gen(devid) >= 6);
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
igt_assert(bufmgr);
// drm_intel_bufmgr_gem_enable_reuse(bufmgr);
target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
igt_assert(target_bo);
}
igt_subtest("normal") {
store_dword_loop(1, 0);
store_dword_loop(2, 0);
store_dword_loop(3, 0);
store_dword_loop(5, 0);
}
igt_subtest("secure-dispatch") {
store_dword_loop(1, SECURE_DISPATCH);
store_dword_loop(2, SECURE_DISPATCH);
store_dword_loop(3, SECURE_DISPATCH);
store_dword_loop(5, SECURE_DISPATCH);
}
igt_subtest("cached-mapping") {
gem_set_caching(fd, target_bo->handle, 1);
store_dword_loop(1, 0);
store_dword_loop(2, 0);
store_dword_loop(3, 0);
store_dword_loop(5, 0);
}
igt_subtest("uncached-mapping") {
gem_set_caching(fd, target_bo->handle, 0);
store_dword_loop(1, 0);
store_dword_loop(2, 0);
store_dword_loop(3, 0);
store_dword_loop(5, 0);
}
igt_fixture {
drm_intel_bo_unreference(target_bo);
drm_intel_bufmgr_destroy(bufmgr);
close(fd);
}
}
/*
* Copyright © 2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
* Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
*
*/
#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
#include "drm.h"
IGT_TEST_DESCRIPTION("Basic CS check using MI_STORE_DATA_IMM.");
#define LOCAL_I915_EXEC_VEBOX (4<<0)
static int devid;
/*
* Testcase: Basic bsd MI check using MI_STORE_DATA_IMM
*/
static unsigned coherent_domain;
static void *
mmap_coherent(int fd, uint32_t handle, int size)
{
if (gem_has_llc(fd)) {
coherent_domain = I915_GEM_DOMAIN_CPU;
return gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
} else if (gem_mmap__has_wc(fd)) {
coherent_domain = I915_GEM_DOMAIN_WC;
return gem_mmap__wc(fd, handle, 0, size, PROT_WRITE);
} else {
coherent_domain = I915_GEM_DOMAIN_GTT;
return gem_mmap__gtt(fd, handle, size, PROT_WRITE);
}
}
static void
store_dword_loop(int fd, int ring, int divider)
{
int i, val = 0;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_relocation_entry reloc[divider];
uint32_t handle[divider];
uint32_t *batch[divider];
uint32_t *target;
int gen = intel_gen(devid);
memset(obj, 0, sizeof(obj));
obj[0].handle = gem_create(fd, 4096);
target = mmap_coherent(fd, obj[0].handle, 4096);
memset(reloc, 0, sizeof(reloc));
for (i = 0; i < divider; i++) {
uint32_t *b;
handle[i] = gem_create(fd, 4096);
batch[i] = mmap_coherent(fd, handle[i], 4096);
gem_set_domain(fd, handle[i], coherent_domain, coherent_domain);
b = batch[i];
*b++ = MI_STORE_DWORD_IMM;
*b++ = 0;
*b++ = 0;
*b++ = 0;
*b++ = MI_BATCH_BUFFER_END;
reloc[i].target_handle = obj[0].handle;
reloc[i].offset = 4;
if (gen < 8)
reloc[i].offset += 4;
reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
obj[1].relocation_count = 1;
}
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.buffer_count = 2;
execbuf.flags = ring;
igt_info("running storedw loop on render with stall every %i batch\n", divider);
for (i = 0; i < SLOW_QUICK(0x2000, 0x10); i++) {
int j = i % divider;
gem_set_domain(fd, handle[j], coherent_domain, coherent_domain);
batch[j][3] = val;
obj[1].handle = handle[j];
obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
gem_execbuf(fd, &execbuf);
if (j == 0) {
gem_set_domain(fd, obj[0].handle, coherent_domain, 0);
igt_assert_f(*target == val,
"%d: value mismatch: stored 0x%08x, expected 0x%08x\n",
i, *target, val);
}
val++;
}
gem_set_domain(fd, obj[0].handle, coherent_domain, 0);
igt_info("completed %d writes successfully, current value: 0x%08x\n",
i, target[0]);
munmap(target, 4096);
gem_close(fd, obj[0].handle);
for (i = 0; i < divider; ++i) {
munmap(batch[i], 4096);
gem_close(fd, handle[i]);
}
}
static void
store_test(int fd, int ring)
{
gem_require_ring(fd, ring);
store_dword_loop(fd, ring, 1);
store_dword_loop(fd, ring, 2);
if (!igt_run_in_simulation()) {
store_dword_loop(fd, ring, 3);
store_dword_loop(fd, ring, 5);
store_dword_loop(fd, ring, 7);
store_dword_loop(fd, ring, 11);
store_dword_loop(fd, ring, 13);
store_dword_loop(fd, ring, 17);
store_dword_loop(fd, ring, 19);
}
}
static void
check_test_requirements(int fd, int ringid)
{
gem_require_ring(fd, ringid);
igt_require(gem_can_store_dword(fd, ringid));
}
igt_main
{
const struct intel_execution_engine *e;
int fd;
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
devid = intel_get_drm_devid(fd);
igt_skip_on_f(intel_gen(devid) < 6,
"MI_STORE_DATA can only use GTT address on gen4+/g33 and "
"needs snoopable mem on pre-gen6\n");
/* This only works with ppgtt */
igt_require(gem_uses_ppgtt(fd));
}
for (e = intel_execution_engines; e->name; e++) {
igt_subtest_f("store-%s", e->name) {
check_test_requirements(fd, e->exec_id);
store_test(fd, eb_ring(e));
}
}
igt_fixture {
close(fd);
}
}
......@@ -196,8 +196,6 @@ i915_progs = [
'gem_softpin',
'gem_spin_batch',
'gem_stolen',
'gem_storedw_batches_loop',
'gem_storedw_loop',
'gem_streaming_writes',
'gem_sync',
'gem_threaded_access_tiled',
......
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