Commit 55a17bc2 authored by Chris Wilson's avatar Chris Wilson 🤔

igt/perf_pmu: Reduce arbitrary delays before rc6

gem_quiescent_gpu() is supposed to ensure that the HW is idle, and in
the process kick the GPU into rc6, so we should not need a long delay
afterwards to ensure that we are indeed in rc6. We do however need a
small delay in order to be sure that rc6 cycle counter has started and
stopped.

v2: Apply to rc6p as well.
v3: The longest rc6 timeout (before the HW kicks in and enables rc6 on
an idle GPU) is 50ms, so make sure that at least that time has passed
since we were busy.
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin's avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent a1e444f4
......@@ -996,7 +996,7 @@ test_rc6(int gem_fd)
fd = open_pmu(I915_PMU_RC6_RESIDENCY);
gem_quiescent_gpu(gem_fd);
usleep(1e6);
usleep(100e3); /* wait for the rc6 cycle counter to kick in */
/* Go idle and check full RC6. */
prev = pmu_read_single(fd);
......@@ -1008,6 +1008,7 @@ test_rc6(int gem_fd)
/* Wake up device and check no RC6. */
fw = igt_open_forcewake_handle(gem_fd);
igt_assert(fw >= 0);
usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
prev = pmu_read_single(fd);
usleep(duration_ns / 1000);
......@@ -1040,7 +1041,7 @@ test_rc6p(int gem_fd)
igt_require(num_pmu == 3);
gem_quiescent_gpu(gem_fd);
usleep(1e6);
usleep(100e3); /* wait for the rc6 cycle counter to kick in */
/* Go idle and check full RC6. */
pmu_read_multi(fd, num_pmu, prev);
......@@ -1053,6 +1054,7 @@ test_rc6p(int gem_fd)
/* Wake up device and check no RC6. */
fw = igt_open_forcewake_handle(gem_fd);
igt_assert(fw >= 0);
usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
pmu_read_multi(fd, num_pmu, prev);
usleep(duration_ns / 1000);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment