Commit 4c57ff46 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Chris Wilson

intel/pmu: Catch-up with i915 RC6 aggregation changes

Since i915 PMU is removing separate RC6 counters and now aggregates all
under a single one, catch up the test and intel-gpu-overlay with those
changes.
Signed-off-by: Tvrtko Ursulin's avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson's avatarChris Wilson <chris@chris-wilson.co.uk>
parent c6577473
......@@ -64,10 +64,8 @@ enum drm_i915_pmu_engine_sample {
#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
#define I915_PMU_RC6p_RESIDENCY __I915_PMU_OTHER(4)
#define I915_PMU_RC6pp_RESIDENCY __I915_PMU_OTHER(5)
#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY
#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
static inline int
perf_event_open(struct perf_event_attr *attr,
......
......@@ -35,34 +35,12 @@
#include "rc6.h"
#define RC6 (1<<0)
#define RC6p (1<<1)
#define RC6pp (1<<2)
static int perf_open(unsigned *flags)
{
int fd;
fd = perf_i915_open_group(I915_PMU_RC6_RESIDENCY, -1);
if (fd < 0)
return -1;
*flags |= RC6;
if (perf_i915_open_group(I915_PMU_RC6p_RESIDENCY, fd) >= 0)
*flags |= RC6p;
if (perf_i915_open_group(I915_PMU_RC6pp_RESIDENCY, fd) >= 0)
*flags |= RC6pp;
return fd;
}
int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
rc6->fd = perf_open(&rc6->flags);
if (rc6->fd == -1) {
rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
return rc6->error = errno;
......@@ -110,7 +88,7 @@ int rc6_update(struct rc6 *rc6)
if (rc6->error)
return rc6->error;
if (rc6->fd == -1) {
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power/rc6_residency_ms", &st) < 0)
......@@ -121,22 +99,13 @@ int rc6_update(struct rc6 *rc6)
s->rc6pp_residency = file_to_u64("/sys/class/drm/card0/power/rc6pp_residency_ms");
s->timestamp = clock_ms_to_u64();
} else {
uint64_t data[5];
int len;
uint64_t data[2];
len = read(rc6->fd, data, sizeof(data));
if (len < 0)
if (read(rc6->fd, data, sizeof(data)) < sizeof(data))
return rc6->error = errno;
s->timestamp = data[1] / (1000*1000);
len = 2;
if (rc6->flags & RC6)
s->rc6_residency = data[len++] / 1e6;
if (rc6->flags & RC6p)
s->rc6p_residency = data[len++] / 1e6;
if (rc6->flags & RC6pp)
s->rc6pp_residency = data[len++] / 1e6;
s->timestamp = data[1] / 1e6;
s->rc6_residency = data[0] / 1e6;
}
if (rc6->count == 1)
......
......@@ -1019,53 +1019,6 @@ test_rc6(int gem_fd)
assert_within_epsilon(busy - prev, 0.0, tolerance);
}
static void
test_rc6p(int gem_fd)
{
int64_t duration_ns = 2e9;
unsigned int num_pmu = 1;
uint64_t idle[3], busy[3], prev[3];
unsigned int slept, i;
int fd, ret, fw;
fd = open_group(I915_PMU_RC6_RESIDENCY, -1);
ret = perf_i915_open_group(I915_PMU_RC6p_RESIDENCY, fd);
if (ret > 0) {
num_pmu++;
ret = perf_i915_open_group(I915_PMU_RC6pp_RESIDENCY, fd);
if (ret > 0)
num_pmu++;
}
igt_require(num_pmu == 3);
gem_quiescent_gpu(gem_fd);
usleep(100e3); /* wait for the rc6 cycle counter to kick in */
/* Go idle and check full RC6. */
pmu_read_multi(fd, num_pmu, prev);
slept = measured_usleep(duration_ns / 1000);
pmu_read_multi(fd, num_pmu, idle);
for (i = 0; i < num_pmu; i++)
assert_within_epsilon(idle[i] - prev[i], slept, tolerance);
/* Wake up device and check no RC6. */
fw = igt_open_forcewake_handle(gem_fd);
igt_assert(fw >= 0);
usleep(1e3); /* wait for the rc6 cycle counter to stop ticking */
pmu_read_multi(fd, num_pmu, prev);
usleep(duration_ns / 1000);
pmu_read_multi(fd, num_pmu, busy);
close(fw);
close(fd);
for (i = 0; i < num_pmu; i++)
assert_within_epsilon(busy[i] - prev[i], 0.0, tolerance);
}
igt_main
{
const unsigned int num_other_metrics =
......@@ -1205,12 +1158,6 @@ igt_main
igt_subtest("rc6")
test_rc6(fd);
/**
* Test RC6p residency reporting.
*/
igt_subtest("rc6p")
test_rc6p(fd);
/**
* Check render nodes are counted.
*/
......
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