Commit 43779e37 authored by Daniel Vetter's avatar Daniel Vetter

tests: merge gem_*_concurrent_blt together

Too much copy&pasting isn't good.
Signed-off-by: Daniel Vetter's avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f542b097
......@@ -11,7 +11,7 @@ gem_bad_blit
gem_bad_length
gem_basic
gem_caching
gem_cpu_concurrent_blit
gem_concurrent_blit
gem_cpu_reloc
gem_cs_prefetch
gem_cs_tlb
......@@ -32,7 +32,6 @@ gem_fenced_exec_thrash
gem_fence_thrash
gem_flink
gem_flink_race
gem_gtt_concurrent_blit
gem_gtt_cpu_tlb
gem_gtt_speed
gem_hang
......@@ -49,7 +48,6 @@ gem_pin
gem_pipe_control_store_loop
gem_pread
gem_pread_after_blit
gem_prw_concurrent_blit
gem_pwrite
gem_pwrite_pread
gem_readwrite
......
......@@ -18,7 +18,7 @@ endif
TESTS_progs_M = \
gem_basic \
gem_caching \
gem_cpu_concurrent_blit \
gem_concurrent_blit \
gem_cs_tlb \
gem_ctx_bad_exec \
gem_dummy_reloc_loop \
......@@ -27,13 +27,11 @@ TESTS_progs_M = \
gem_fence_thrash \
gem_flink \
gem_flink_race \
gem_gtt_concurrent_blit \
gem_linear_blits \
gem_mmap_gtt \
gem_partial_pwrite_pread \
gem_pread \
gem_pread_after_blit \
gem_prw_concurrent_blit \
gem_pwrite \
gem_pwrite_pread \
gem_readwrite \
......
......@@ -27,7 +27,7 @@
*
*/
/** @file gem_prw_concurrent_blit.c
/** @file gem_concurrent_blit.c
*
* This is a test of pread/pwrite behavior when writing to active
* buffers.
......@@ -52,7 +52,7 @@
#include "intel_gpu_tools.h"
static void
set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
prw_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr, *tmp;
......@@ -65,7 +65,7 @@ set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
}
static void
cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
prw_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr, *tmp;
......@@ -78,7 +78,7 @@ cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
}
static drm_intel_bo *
create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
unmapped_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
{
drm_intel_bo *bo;
......@@ -88,123 +88,195 @@ create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
return bo;
}
int
main(int argc, char **argv)
static void
gtt_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
int num_buffers = 128, max;
drm_intel_bo *src[128], *dst[128], *dummy = NULL;
int width = 512, height = 512;
int fd, loop, i, nc;
pid_t children[16];
int size = width * height;
uint32_t *vaddr;
igt_subtest_init(argc, argv);
igt_skip_on_simulation();
drm_intel_gem_bo_start_gtt_access(bo, true);
vaddr = bo->virtual;
while (size--)
*vaddr++ = val;
}
fd = drm_open_any();
static void
gtt_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr;
max = gem_aperture_size (fd) / (1024 * 1024) / 2;
if (num_buffers > max)
num_buffers = max;
drm_intel_gem_bo_start_gtt_access(bo, false);
vaddr = bo->virtual;
while (size--)
igt_assert(*vaddr++ == val);
}
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
static drm_intel_bo *
gtt_create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
{
drm_intel_bo *bo;
bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
igt_assert(bo);
/* gtt map doesn't have a write parameter, so just keep the mapping
* around (to avoid the set_domain with the gtt write domain set) and
* manually tell the kernel when we start access the gtt. */
do_or_die(drm_intel_gem_bo_map_gtt(bo));
return bo;
}
static void
cpu_set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr;
do_or_die(drm_intel_bo_map(bo, true));
vaddr = bo->virtual;
while (size--)
*vaddr++ = val;
drm_intel_bo_unmap(bo);
}
static void
cpu_cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr;
do_or_die(drm_intel_bo_map(bo, false));
vaddr = bo->virtual;
while (size--)
igt_assert(*vaddr++ == val);
drm_intel_bo_unmap(bo);
}
struct access_mode {
void (*set_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
void (*cmp_bo)(drm_intel_bo *bo, uint32_t val, int w, int h);
drm_intel_bo *(*create_bo)(drm_intel_bufmgr *bufmgr,
uint32_t val, int width, int height);
const char *name;
};
struct access_mode access_modes[] = {
{ .set_bo = prw_set_bo, .cmp_bo = prw_cmp_bo,
.create_bo = unmapped_create_bo, .name = "prw" },
{ .set_bo = cpu_set_bo, .cmp_bo = cpu_cmp_bo,
.create_bo = unmapped_create_bo, .name = "cpu" },
{ .set_bo = gtt_set_bo, .cmp_bo = gtt_cmp_bo,
.create_bo = gtt_create_bo, .name = "gtt" },
};
int num_buffers = 128, fd;
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
static void
run_modes(struct access_mode *mode)
{
int width = 512, height = 512;
int loop, i, nc;
pid_t children[16];
drm_intel_bo *src[128], *dst[128], *dummy = NULL;
if (!igt_only_list_subtests()) {
for (i = 0; i < num_buffers; i++) {
src[i] = create_bo(bufmgr, i, width, height);
dst[i] = create_bo(bufmgr, ~i, width, height);
src[i] = mode->create_bo(bufmgr, i, width, height);
dst[i] = mode->create_bo(bufmgr, ~i, width, height);
}
dummy = create_bo(bufmgr, 0, width, height);
dummy = mode->create_bo(bufmgr, 0, width, height);
}
/* try to overwrite the source values */
igt_subtest("overwrite-source") {
igt_subtest_f("%s-overwrite-source", mode->name) {
for (i = 0; i < num_buffers; i++) {
set_bo(src[i], i, width, height);
set_bo(dst[i], i, width, height);
mode->set_bo(src[i], i, width, height);
mode->set_bo(dst[i], i, width, height);
}
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
mode->set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
cmp_bo(dst[i], i, width, height);
mode->cmp_bo(dst[i], i, width, height);
}
/* try to read the results before the copy completes */
igt_subtest("early-read") {
igt_subtest_f("%s-early-read", mode->name) {
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
mode->set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xdeadbeef, width, height);
mode->cmp_bo(dst[i], 0xdeadbeef, width, height);
}
/* and finally try to trick the kernel into loosing the pending write */
igt_subtest("gpu-read-after-write") {
igt_subtest_f("%s-gpu-read-after-write", mode->name) {
for (i = num_buffers; i--; )
set_bo(src[i], 0xabcdabcd, width, height);
mode->set_bo(src[i], 0xabcdabcd, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
intel_copy_bo(batch, dummy, dst[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xabcdabcd, width, height);
mode->cmp_bo(dst[i], 0xabcdabcd, width, height);
}
igt_fork_signal_helper();
/* try to read the results before the copy completes */
igt_subtest("overwrite-source-interruptible") {
igt_subtest_f("%s-overwrite-source-interruptible", mode->name) {
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = 0; i < num_buffers; i++) {
set_bo(src[i], i, width, height);
set_bo(dst[i], i, width, height);
mode->set_bo(src[i], i, width, height);
mode->set_bo(dst[i], i, width, height);
}
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
mode->set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
cmp_bo(dst[i], i, width, height);
mode->cmp_bo(dst[i], i, width, height);
}
}
/* try to read the results before the copy completes */
igt_subtest("early-read-interruptible") {
igt_subtest_f("%s-early-read-interruptible", mode->name) {
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
mode->set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xdeadbeef, width, height);
mode->cmp_bo(dst[i], 0xdeadbeef, width, height);
}
}
/* and finally try to trick the kernel into loosing the pending write */
igt_subtest("gpu-read-after-write-interruptible") {
igt_subtest_f("%s-gpu-read-after-write-interruptible", mode->name) {
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = num_buffers; i--; )
set_bo(src[i], 0xabcdabcd, width, height);
mode->set_bo(src[i], 0xabcdabcd, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
intel_copy_bo(batch, dummy, dst[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xabcdabcd, width, height);
mode->cmp_bo(dst[i], 0xabcdabcd, width, height);
}
}
/* try to read the results before the copy completes */
igt_subtest("overwrite-source-forked") {
igt_subtest_f("%s-overwrite-source-forked", mode->name) {
for (nc = 0; nc < ARRAY_SIZE(children); nc++) {
switch ((children[nc] = fork())) {
case -1: igt_assert(0);
......@@ -215,21 +287,21 @@ main(int argc, char **argv)
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
for (i = 0; i < num_buffers; i++) {
src[i] = create_bo(bufmgr, i, width, height);
dst[i] = create_bo(bufmgr, ~i, width, height);
src[i] = mode->create_bo(bufmgr, i, width, height);
dst[i] = mode->create_bo(bufmgr, ~i, width, height);
}
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = 0; i < num_buffers; i++) {
set_bo(src[i], i, width, height);
set_bo(dst[i], i, width, height);
mode->set_bo(src[i], i, width, height);
mode->set_bo(dst[i], i, width, height);
}
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
mode->set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
cmp_bo(dst[i], i, width, height);
mode->cmp_bo(dst[i], i, width, height);
}
exit(0);
}
......@@ -244,7 +316,7 @@ main(int argc, char **argv)
}
/* try to read the results before the copy completes */
igt_subtest("early-read-forked") {
igt_subtest_f("%s-early-read-forked", mode->name) {
for (nc = 0; nc < ARRAY_SIZE(children); nc++) {
switch ((children[nc] = fork())) {
case -1: igt_assert(0);
......@@ -255,17 +327,17 @@ main(int argc, char **argv)
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
for (i = 0; i < num_buffers; i++) {
src[i] = create_bo(bufmgr, i, width, height);
dst[i] = create_bo(bufmgr, ~i, width, height);
src[i] = mode->create_bo(bufmgr, i, width, height);
dst[i] = mode->create_bo(bufmgr, ~i, width, height);
}
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
mode->set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xdeadbeef, width, height);
mode->cmp_bo(dst[i], 0xdeadbeef, width, height);
}
exit(0);
}
......@@ -280,7 +352,7 @@ main(int argc, char **argv)
}
/* and finally try to trick the kernel into loosing the pending write */
igt_subtest("gpu-read-after-write-forked") {
igt_subtest_f("%s-gpu-read-after-write-forked", mode->name) {
for (nc = 0; nc < ARRAY_SIZE(children); nc++) {
switch ((children[nc] = fork())) {
case -1: igt_assert(0);
......@@ -291,20 +363,20 @@ main(int argc, char **argv)
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
for (i = 0; i < num_buffers; i++) {
src[i] = create_bo(bufmgr, i, width, height);
dst[i] = create_bo(bufmgr, ~i, width, height);
src[i] = mode->create_bo(bufmgr, i, width, height);
dst[i] = mode->create_bo(bufmgr, ~i, width, height);
}
dummy = create_bo(bufmgr, 0, width, height);
dummy = mode->create_bo(bufmgr, 0, width, height);
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = num_buffers; i--; )
set_bo(src[i], 0xabcdabcd, width, height);
mode->set_bo(src[i], 0xabcdabcd, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
intel_copy_bo(batch, dummy, dst[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xabcdabcd, width, height);
mode->cmp_bo(dst[i], 0xabcdabcd, width, height);
}
exit(0);
}
......@@ -320,5 +392,35 @@ main(int argc, char **argv)
igt_stop_signal_helper();
if (!igt_only_list_subtests()) {
for (i = 0; i < num_buffers; i++) {
drm_intel_bo_unreference(src[i]);
drm_intel_bo_unreference(dst[i]);
}
drm_intel_bo_unreference(dummy);
}
}
int
main(int argc, char **argv)
{
int max, i;
igt_subtest_init(argc, argv);
igt_skip_on_simulation();
fd = drm_open_any();
max = gem_aperture_size (fd) / (1024 * 1024) / 2;
if (num_buffers > max)
num_buffers = max;
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
for (i = 0; i < ARRAY_SIZE(access_modes); i++)
run_modes(&access_modes[i]);
return 0;
}
/*
* Copyright © 2009,2012 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
* Chris Wilson <chris@chris-wilson.co.uk>
*
*/
/** @file gem_cpu_concurrent_blit.c
*
* This is a test of CPU read/write behavior when writing to active
* buffers.
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/wait.h>
#include "drm.h"
#include "i915_drm.h"
#include "drmtest.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#include "intel_gpu_tools.h"
static void
set_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr;
do_or_die(drm_intel_bo_map(bo, true));
vaddr = bo->virtual;
while (size--)
*vaddr++ = val;
drm_intel_bo_unmap(bo);
}
static void
cmp_bo(drm_intel_bo *bo, uint32_t val, int width, int height)
{
int size = width * height;
uint32_t *vaddr;
do_or_die(drm_intel_bo_map(bo, false));
vaddr = bo->virtual;
while (size--)
igt_assert(*vaddr++ == val);
drm_intel_bo_unmap(bo);
}
static drm_intel_bo *
create_bo(drm_intel_bufmgr *bufmgr, uint32_t val, int width, int height)
{
drm_intel_bo *bo;
bo = drm_intel_bo_alloc(bufmgr, "bo", 4*width*height, 0);
igt_assert(bo);
return bo;
}
int
main(int argc, char **argv)
{
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
int num_buffers = 128, max;
drm_intel_bo *src[128], *dst[128], *dummy = NULL;
int width = 512, height = 512;
int i, loop, fd, nc;
pid_t children[16];
igt_subtest_init(argc, argv);
igt_skip_on_simulation();
fd = drm_open_any();
max = gem_aperture_size (fd) / (1024 * 1024) / 2;
if (num_buffers > max)
num_buffers = max;
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
drm_intel_bufmgr_gem_enable_reuse(bufmgr);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
if (!igt_only_list_subtests()) {
for (i = 0; i < num_buffers; i++) {
src[i] = create_bo(bufmgr, i, width, height);
dst[i] = create_bo(bufmgr, ~i, width, height);
}
dummy = create_bo(bufmgr, 0, width, height);
}
/* try to overwrite the source values */
igt_subtest("overwrite-source") {
for (i = 0; i < num_buffers; i++) {
set_bo(src[i], i, width, height);
set_bo(dst[i], i, width, height);
}
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
cmp_bo(dst[i], i, width, height);
}
/* try to read the results before the copy completes */
igt_subtest("early-read") {
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xdeadbeef, width, height);
}
/* and finally try to trick the kernel into loosing the pending write */
igt_subtest("gpu-read-after-write") {
for (i = num_buffers; i--; )
set_bo(src[i], 0xabcdabcd, width, height);
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
intel_copy_bo(batch, dummy, dst[i], width, height);
for (i = num_buffers; i--; )
cmp_bo(dst[i], 0xabcdabcd, width, height);
}
igt_fork_signal_helper();
/* try to overwrite the source values */
igt_subtest("overwrite-source-interruptible") {
for (loop = 0; loop < 10; loop++) {
gem_quiescent_gpu(fd);
for (i = 0; i < num_buffers; i++) {
set_bo(src[i], i, width, height);
set_bo(dst[i], i, width, height);
}
for (i = 0; i < num_buffers; i++)
intel_copy_bo(batch, dst[i], src[i], width, height);
for (i = num_buffers; i--; )
set_bo(src[i], 0xdeadbeef, width, height);
for (i = 0; i < num_buffers; i++)
cmp_bo(dst[i], i, width, height);
}
}
/* try to read the results before the copy completes */