<7> [366.738906] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_C
<7> [366.739042] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_D
<7> [366.739302] PM: early resume of devices complete after 3.623 msecs
<6> [366.739934] ACPI: EC: event unblocked
<4> [366.740922] xhci_hcd 0000:02:00.0: xHC error in resume, USBSTS 0x401, Reinit
<5> [366.740930] usb usb3: root hub lost power or was reset
<5> [366.740932] usb usb4: root hub lost power or was reset
<6> [366.741553] i915 0000:00:02.0: [drm] GT0: GuC firmware i915/skl_guc_70.1.1.bin version 70.1.1
<6> [366.741559] i915 0000:00:02.0: [drm] GT0: HuC firmware i915/skl_huc_2.0.0.bin version 2.0.0
<6> [366.747709] serial 00:01: activated
<7> [366.756398] i915 0000:00:02.0: [drm:intel_guc_fw_upload [i915]] GT0: GUC: init took 11ms, freq = 100MHz, before = 100MHz, status = 0x8002F0EC, count = 0, ret = 0
<7> [366.757379] i915 0000:00:02.0: [drm:guc_enable_communication [i915]] GT0: GUC: communication enabled
<6> [366.767397] i915 0000:00:02.0: [drm] GT0: HuC: authenticated for all workloads
<6> [366.767401] i915 0000:00:02.0: [drm] GT0: GUC: submission disabled
<6> [366.767404] i915 0000:00:02.0: [drm] GT0: GUC: SLPC disabled
<7> [366.767993] i915 0000:00:02.0: [drm:intel_cdclk_dump_config [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
<7> [366.768268] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:51:pipe A] hw state readout: disabled
<7> [366.768424] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:72:pipe B] hw state readout: disabled
<7> [366.768580] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:93:pipe C] hw state readout: disabled
<7> [366.768717] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] hw state readout: disabled, pipe A
<7> [366.768868] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] hw state readout: disabled, pipe A
<7> [366.769004] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] hw state readout: disabled, pipe A
<7> [366.769140] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] hw state readout: disabled, pipe B
<7> [366.769276] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] hw state readout: disabled, pipe B
<7> [366.769410] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] hw state readout: disabled, pipe B
<7> [366.769545] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] hw state readout: disabled, pipe C
<7> [366.769680] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] hw state readout: disabled, pipe C
<7> [366.769829] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] hw state readout: disabled, pipe C
<7> [366.769966] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:94:DDI B/PHY B] hw state readout: disabled, pipe A
<7> [366.770102] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:103:DDI C/PHY C] hw state readout: disabled, pipe A
<7> [366.770238] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:107:DDI D/PHY D] hw state readout: disabled, pipe A
<7> [366.770367] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:109:DP-MST A] hw state readout: disabled, pipe A
<7> [366.770496] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:110:DP-MST B] hw state readout: disabled, pipe B
<7> [366.770625] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:111:DP-MST C] hw state readout: disabled, pipe C
<7> [366.770768] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:118:DDI E/PHY E] hw state readout: disabled, pipe A
<7> [366.770906] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 0 hw state readout: pipe_mask 0x0, on 1
<7> [366.771046] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 1 hw state readout: pipe_mask 0x0, on 0
<7> [366.771186] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 2 hw state readout: pipe_mask 0x0, on 0
<7> [366.771326] i915 0000:00:02.0: [drm:intel_dpll_readout_hw_state [i915]] DPLL 3 hw state readout: pipe_mask 0x0, on 0
<7> [366.771471] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:95:HDMI-A-1] hw state readout: disabled
<7> [366.771611] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:104:HDMI-A-2] hw state readout: disabled
<7> [366.771762] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:108:DP-1] hw state readout: disabled
<7> [366.771902] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:115:HDMI-A-3] hw state readout: disabled
<7> [366.772043] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:119:DP-2] hw state readout: disabled
<7> [366.772173] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] min_cdclk 0 kHz
<7> [366.772302] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] min_cdclk 0 kHz
<7> [366.772430] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] min_cdclk 0 kHz
<7> [366.772559] i915 0000:00:02.0: [drm:intel_bw_crtc_update [i915]] pipe A data rate 0 num active planes 0
<7> [366.772694] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] min_cdclk 0 kHz
<7> [366.772832] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] min_cdclk 0 kHz
<7> [366.772961] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] min_cdclk 0 kHz
<7> [366.773090] i915 0000:00:02.0: [drm:intel_bw_crtc_update [i915]] pipe B data rate 0 num active planes 0
<7> [366.773224] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] min_cdclk 0 kHz
<7> [366.773354] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] min_cdclk 0 kHz
<7> [366.773483] i915 0000:00:02.0: [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] min_cdclk 0 kHz
<7> [366.773612] i915 0000:00:02.0: [drm:intel_bw_crtc_update [i915]] pipe C data rate 0 num active planes 0
<5> [366.773765] i915 0000:00:02.0: [drm] [ENCODER:94:DDI B/PHY B] is disabled/in DSI mode with an ungated DDI clock, gate it
<5> [366.773776] i915 0000:00:02.0: [drm] [ENCODER:103:DDI C/PHY C] is disabled/in DSI mode with an ungated DDI clock, gate it
<5> [366.773792] i915 0000:00:02.0: [drm] [ENCODER:107:DDI D/PHY D] is disabled/in DSI mode with an ungated DDI clock, gate it
<5> [366.773815] i915 0000:00:02.0: [drm] [ENCODER:118:DDI E/PHY E] is disabled/in DSI mode with an ungated DDI clock, gate it
<7> [366.773824] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:51:pipe A] enable: no [setup_hw_state]
<7> [366.773961] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:72:pipe B] enable: no [setup_hw_state]
<7> [366.774096] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [CRTC:93:pipe C] enable: no [setup_hw_state]
<7> [366.774231] i915 0000:00:02.0: [drm:intel_dpll_sanitize_state [i915]] DPLL 0 enabled but not in use, disabling
<7> [366.774365] i915 0000:00:02.0: [drm:skl_wm_get_hw_state_and_sanitize [i915]] [CRTC:51:pipe A] dbuf slices 0x0, ddb (0 - 0), active pipes 0x0, mbus joined: no
<7> [366.774492] i915 0000:00:02.0: [drm:skl_wm_get_hw_state_and_sanitize [i915]] [CRTC:72:pipe B] dbuf slices 0x0, ddb (0 - 0), active pipes 0x0, mbus joined: no
<7> [366.774619] i915 0000:00:02.0: [drm:skl_wm_get_hw_state_and_sanitize [i915]] [CRTC:93:pipe C] dbuf slices 0x0, ddb (0 - 0), active pipes 0x0, mbus joined: no
<7> [366.774796] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:104:HDMI-A-2] Limiting display bpp to 24 (EDID bpp 0, max requested bpp 36, max platform bpp 36)
<7> [366.774941] i915 0000:00:02.0: [drm:intel_hdmi_compute_clock [i915]] picking 8 bpc for HDMI output (pipe bpp: 24)
<7> [366.775063] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:51:pipe A] hw max bpp: 24, pipe bpp: 24, dithering: 0
<7> [366.775212] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:119:DP-2] Limiting display bpp to 24 (EDID bpp 0, max requested bpp 36, max platform bpp 36)
<7> [366.775348] i915 0000:00:02.0: [drm:intel_dp_compute_config_link_bpp_limits [i915]] [ENCODER:118:DDI E/PHY E][CRTC:72:pipe B] DP link limits: pixel clock 25175 kHz DSC off max lanes 2 max rate 270000 max pipe_bpp 24 max link_bpp 24.0000
<7> [366.775472] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP lane count 1 clock 162000 bpp 24
<7> [366.775592] i915 0000:00:02.0: [drm:intel_dp_compute_link_config [i915]] DP link rate required 75525 available 162000
<7> [366.775713] i915 0000:00:02.0: [drm:intel_dp_audio_compute_config [i915]] [CONNECTOR:119:DP-2] SDP split enable: no
<7> [366.775845] i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CRTC:72:pipe B] hw max bpp: 24, pipe bpp: 24, dithering: 0