igt@kms_vblank@pipe-*-ts-continuation.*-suspend - incomplete - PM: suspend entry (s2idle)

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1397/bat-dg2-8/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

<7> [330.293083] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:235:DDI A/PHY A]
<7> [330.293231] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:237:DP-MST A]
<7> [330.293379] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:238:DP-MST B]
<7> [330.293527] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:239:DP-MST C]
<7> [330.293683] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:240:DP-MST D]
<7> [330.293831] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:248:DDI B/PHY B]
<7> [330.293977] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:250:DP-MST A]
<7> [330.294123] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:251:DP-MST B]
<7> [330.294270] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:252:DP-MST C]
<7> [330.294417] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:253:DP-MST D]
<7> [330.294564] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:263:DDI C/PHY C]
<7> [330.294719] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:265:DP-MST A]
<7> [330.294864] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:266:DP-MST B]
<7> [330.295008] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:267:DP-MST C]
<7> [330.295153] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:268:DP-MST D]
<7> [330.295297] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:275:DDI D/PHY D]
<7> [330.295440] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:277:DP-MST A]
<7> [330.295584] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:278:DP-MST B]
<7> [330.295737] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:279:DP-MST C]
<7> [330.295912] i915 0000:03:00.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:280:DP-MST D]
<7> [330.296058] i915 0000:03:00.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0xd
<7> [330.296340] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling AUX_A
<7> [330.297737] i915 0000:03:00.0: [drm:intel_dp_128b132b_sdp_crc16 [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] DP2.0 SDP CRC16 for 128b/132b enabled
<7> [330.297968] i915 0000:03:00.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_A
<7> [330.304169] i915 0000:03:00.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: Base DPCD: 12 14 c4 81 01 1d 01 81 00 00 04 00 00 00 84
<7> [330.304186] i915 0000:03:00.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: DPCD: 14 1e c4 81 01 1d 01 81 00 00 04 00 00 00 84
<7> [330.305474] i915 0000:03:00.0: [drm:intel_dp_init_lttpr_and_dprx_caps [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] LTTPR common capabilities: 00 00 00 00 00 00 00 00
<7> [330.307997] i915 0000:03:00.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: Base DPCD: 12 14 c4 81 01 1d 01 81 00 00 04 00 00 00 84
<7> [330.308011] i915 0000:03:00.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: DPCD: 14 1e c4 81 01 1d 01 81 00 00 04 00 00 00 84
<7> [330.308895] i915 0000:03:00.0: [drm:intel_dp_start_link_train [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] Using LINK_BW_SET value 14
<7> [330.310274] i915 0000:03:00.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [330.310432] i915 0000:03:00.0: [drm:intel_dp_program_link_training_pattern [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] Using DP training pattern TPS1
<7> [330.314166] i915 0000:03:00.0: [drm:intel_dp_get_adjust_train [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 2/2/2/2, pre-emphasis request: 0/0/0/0
<7> [330.314320] i915 0000:03:00.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 2/2/2/2, pre-emphasis levels: 0/0/0/0
<7> [330.317987] i915 0000:03:00.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] Clock recovery OK
<7> [330.318124] i915 0000:03:00.0: [drm:intel_dp_program_link_training_pattern [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] Using DP training pattern TPS4
<7> [330.351866] i915 0000:03:00.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] Channel EQ done. DP Training successful
<7> [330.352005] i915 0000:03:00.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A][DPRX] Link Training passed at link rate = 540000, lane count = 4
<7> [330.353113] i915 0000:03:00.0: [drm:intel_enable_transcoder [i915]] enabling pipe D
<7> [330.353372] i915 0000:03:00.0: [drm:intel_audio_codec_enable [i915]] [CONNECTOR:236:DP-1][ENCODER:235:DDI A/PHY A] Enable audio codec on [CRTC:233:pipe D], 36 bytes ELD
<7> [330.370088] i915 0000:03:00.0: [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
<7> [330.386751] i915 0000:03:00.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0xd
<7> [330.387313] i915 0000:03:00.0: [drm:verify_connector_state [i915]] [CONNECTOR:236:DP-1]
<7> [330.387515] i915 0000:03:00.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:233:pipe D]
<7> [330.388014] i915 0000:03:00.0: [drm:intel_ddi_get_config [i915]] [ENCODER:235:DDI A/PHY A] Fec status: 0
<7> [330.438374] i915 0000:03:00.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe D
<6> [330.528763] PM: suspend entry (s2idle)
<6> [330.532442] Filesystems sync: 0.003 seconds
<6> [330.540216] Freezing user space processes