igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend - incomplete - PM: suspend entry (s2idle)
<7> [124.257448] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:357:DP-MST C]
<7> [124.257702] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:358:DP-MST D]
<7> [124.257949] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] DPLL 0
<7> [124.258189] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] DPLL 1
<7> [124.258414] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TBT PLL
<7> [124.258640] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 1
<7> [124.259091] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 2
<7> [124.259513] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 3
<7> [124.259978] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 4
<7> [124.260245] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 5
<7> [124.260479] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] TC PLL 6
<7> [124.260777] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [124.261061] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x1
<7> [124.261507] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:308:eDP-1]
<7> [124.262027] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:98:pipe A]
<7> [124.262417] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.35 [i915]] DPLL 0
<7> [124.262700] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC_off
<7> [124.262910] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [124.263073] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.13 [i915]] Setting DC state from 00 to 02
<6> [124.318620] PM: suspend entry (s2idle)
<6> [124.320692] Filesystems sync: 0.002 seconds