igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions(-varying-size)? - incomplete - No warnings/errors

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12234/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

<7> [1263.290388] i915 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: DPCD: 12 0a 84 41 00 00 01 c0 02 03 00 00 00 0b 00
<7> [1263.291915] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] [ENCODER:94:DDI A/PHY A] Using LINK_BW_SET value 0a
<7> [1263.295259] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [1263.296789] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [1263.298231] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Using DP training pattern TPS1
<7> [1263.303043] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Clock recovery OK
<7> [1263.304459] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Using DP training pattern TPS2
<7> [1263.310078] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 0/0/0/0, pre-emphasis request: 1/1/1/1
<7> [1263.311518] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 1/1/1/1
<7> [1263.313035] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 01000000
<7> [1263.319130] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 0/0/0/0, pre-emphasis request: 2/2/2/2
<7> [1263.320600] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 2/2/2/2
<7> [1263.322127] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 02000000
<7> [1263.328051] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 0/0/0/0, pre-emphasis request: 0/0/0/0
<7> [1263.329477] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [1263.331077] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [1263.338098] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Channel EQ done. DP Training successful
<7> [1263.339403] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:95:eDP-1][ENCODER:94:DDI A/PHY A][DPRX] Link Training passed at link rate = 270000, lane count = 4
<7> [1263.342070] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe A
<7> [1263.344112] i915 0000:00:02.0: [drm:intel_edp_backlight_on [i915]] 
<7> [1263.345451] i915 0000:00:02.0: [drm:intel_backlight_enable [i915]] pipe A
<7> [1263.347101] i915 0000:00:02.0: [drm:intel_backlight_set_pwm_level [i915]] set backlight PWM = 187
<7> [1263.361127] i915 0000:00:02.0: [drm:intel_psr_post_plane_update [i915]] Enabling PSR1
<7> [1263.366412] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [1263.368129] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:51:pipe A]
<7> [1263.371228] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [1263.377753] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [1266.397167] i915 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD off
<7> [1266.399005] i915 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
<7> [1266.400653] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC_off
<7> [1266.402277] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [1266.403928] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 02