igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions.* - incomplete - No warnings/errors

https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7002/shard-skl4/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions.html

<7> [1216.227492] i915 0000:00:02.0: [drm:wait_panel_status [i915]] Wait complete
<7> [1216.229114] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_A_E
<7> [1216.237014] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [1216.261059] i915 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD on
<7> [1216.262728] i915 0000:00:02.0: [drm:intel_pps_vdd_on_unlocked [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
<7> [1216.294757] i915 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX A/DDI A/PHY A: DPCD: 12 0a 84 41 00 00 01 c0 02 03 00 00 00 0b 00
<7> [1216.296149] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] [ENCODER:94:DDI A/PHY A] Using LINK_BW_SET value 0a
<7> [1216.320183] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [1216.321961] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [1216.323717] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Using DP training pattern TPS1
<7> [1216.351005] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Clock recovery OK
<7> [1216.357866] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Using DP training pattern TPS2
<7> [1216.368518] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 0/0/0/0, pre-emphasis request: 1/1/1/1
<7> [1216.370009] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 1/1/1/1
<7> [1216.371554] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 01000000
<7> [1216.386562] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 0/0/0/0, pre-emphasis request: 2/2/2/2
<7> [1216.388055] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 2/2/2/2
<7> [1216.390121] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 02000000
<7> [1216.402596] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing request: 0/0/0/0, pre-emphasis request: 0/0/0/0
<7> [1216.404083] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:94:DDI A/PHY A][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [1216.406156] i915 0000:00:02.0: [drm:hsw_set_signal_levels [i915]] Using signal levels 00000000
<7> [1216.420497] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:94:DDI A/PHY A][DPRX] Channel EQ done. DP Training successful
<7> [1216.423559] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:95:eDP-1][ENCODER:94:DDI A/PHY A][DPRX] Link Training passed at link rate = 270000, lane count = 4
<7> [1216.433208] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe A
<7> [1216.435138] i915 0000:00:02.0: [drm:intel_edp_backlight_on [i915]] 
<7> [1216.436650] i915 0000:00:02.0: [drm:intel_backlight_enable [i915]] pipe A
<7> [1216.469884] i915 0000:00:02.0: [drm:intel_backlight_set_pwm_level [i915]] set backlight PWM = 187
<7> [1216.486617] i915 0000:00:02.0: [drm:intel_psr_post_plane_update [i915]] Enabling PSR1
<7> [1216.502059] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:95:eDP-1]
<7> [1216.504632] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:51:pipe A]
<7> [1216.507829] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [1216.515136] i915 0000:00:02.0: [drm:i915_fifo_underrun_reset_write [i915]] Re-arming FIFO underruns on pipe A
<7> [1219.558652] i915 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [i915]] Turning [ENCODER:94:DDI A/PHY A] VDD off
<7> [1219.560512] i915 0000:00:02.0: [drm:intel_pps_vdd_off_sync_unlocked [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
<7> [1219.561908] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC_off
<7> [1219.563494] i915 0000:00:02.0: [drm:skl_enable_dc6 [i915]] Enabling DC6
<7> [1219.564964] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 00 to 02