igt@kms_flip@.*flip-vs-suspend(-interruptible)?.* - incomplete - PM: suspend entry (deep)

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11985/re-dg2-12/igt@kms_flip@flip-vs-suspend-interruptible.html

<7> [207.040428] i915 0000:03:00.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:275:DDI D/PHY D][DPRX] 8b/10b, lanes: 4, vswing request: 1/1/1/1, pre-emphasis request: 0/0/0/0
<7> [207.040656] i915 0000:03:00.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:275:DDI D/PHY D][DPRX] 8b/10b, lanes: 4, vswing levels: 1/1/1/1, pre-emphasis levels: 0/0/0/0
<7> [207.043774] i915 0000:03:00.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:275:DDI D/PHY D][DPRX] 8b/10b, lanes: 4, vswing request: 2/2/2/2, pre-emphasis request: 0/0/0/0
<7> [207.043968] i915 0000:03:00.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:275:DDI D/PHY D][DPRX] 8b/10b, lanes: 4, vswing levels: 2/2/2/2, pre-emphasis levels: 0/0/0/0
<7> [207.047649] i915 0000:03:00.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:275:DDI D/PHY D][DPRX] Clock recovery OK
<7> [207.047828] i915 0000:03:00.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:275:DDI D/PHY D][DPRX] Using DP training pattern TPS3
<7> [207.051431] i915 0000:03:00.0: [drm:intel_dp_get_adjust_train [i915]] [ENCODER:275:DDI D/PHY D][DPRX] 8b/10b, lanes: 4, vswing request: 3/3/3/3, pre-emphasis request: 0/0/0/0
<7> [207.051598] i915 0000:03:00.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:275:DDI D/PHY D][DPRX] 8b/10b, lanes: 4, vswing levels: 3(max)/3(max)/3(max)/3(max), pre-emphasis levels: 0/0/0/0
<7> [207.055876] i915 0000:03:00.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:275:DDI D/PHY D][DPRX] Channel EQ done. DP Training successful
<7> [207.056023] i915 0000:03:00.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:276:DP-4][ENCODER:275:DDI D/PHY D][DPRX] Link Training passed at link rate = 540000, lane count = 4
<7> [207.056851] i915 0000:03:00.0: [drm:intel_enable_transcoder [i915]] enabling pipe B
<7> [207.057114] i915 0000:03:00.0: [drm:intel_audio_codec_enable [i915]] [CONNECTOR:276:DP-4][ENCODER:275:DDI D/PHY D] Enable audio codec on pipe B, 36 bytes ELD
<7> [207.057323] i915 0000:03:00.0: [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
<7> [207.074050] i915 0000:03:00.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [207.074596] i915 0000:03:00.0: [drm:verify_connector_state [i915]] [CONNECTOR:276:DP-4]
<7> [207.074801] i915 0000:03:00.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:131:pipe B]
<7> [207.075240] i915 0000:03:00.0: [drm:intel_ddi_get_config [i915]] [ENCODER:275:DDI D/PHY D] Fec status: 0
<6> [207.143981] PM: suspend entry (deep)
<6> [207.144857] Filesystems sync: 0.000 seconds