<7> [215.651839] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] vrr: no, vmin: 0, vmax: 0, pipeline full: 0, guardband: 0 flipline: 0, vmin vblank: -1, vmax vblank: -2
<7> [215.651919] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] requested mode: "1920x1080": 60 148500 1920 2008 2052 2200 1080 1083 1088 1125 0x48 0x9
<7> [215.651991] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] adjusted mode: "1920x1080": 60 148500 1920 2008 2052 2200 1080 1083 1088 1125 0x48 0x9
<7> [215.652065] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1083 1088 1125, type: 0x48 flags: 0x9
<7> [215.652139] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] pipe mode: "1920x1080": 60 148500 1920 2008 2052 2200 1080 1083 1088 1125 0x40 0x9
<7> [215.652211] i915 0000:00:02.0: [drm:intel_dump_crtc_timings [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1083 1088 1125, type: 0x40 flags: 0x9
<7> [215.652281] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] port clock: 222750, pipe src: 1920x1080+0+0, pixel rate 148500
<7> [215.652350] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] linetime: 119, ips linetime: 0
<7> [215.652418] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
<7> [215.652489] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] pch pfit: 0x0+0+0, disabled, force thru: no
<7> [215.652561] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] ips: 0, double wide: 0, drrs: 0
<7> [215.652633] i915 0000:00:02.0: [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x800173, cfgcr1: 0xa84, div0: 0x0, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0
<7> [215.652707] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0
<7> [215.652780] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] degamma lut: 0 entries, gamma lut: 0 entries
<7> [215.652852] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:82:plane 1B] fb: [FB:208] 3840x2160 format = XR24 little-endian (0x34325258) modifier = 0x0, visible: yes
<7> [215.652933] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] rotation: 0x1, scaler: -1
<7> [215.653004] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] src: 1920.000000x1080.000000+1152.000000+5.000000 dst: 1920x1080+0+0
<7> [215.653076] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:91:plane 2B] fb: [NOFB], visible: no
<7> [215.653147] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:100:plane 3B] fb: [NOFB], visible: no
<7> [215.653220] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:109:plane 4B] fb: [NOFB], visible: no
<7> [215.653289] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:118:plane 5B] fb: [NOFB], visible: no
<7> [215.653357] i915 0000:00:02.0: [drm:intel_crtc_state_dump [i915]] [PLANE:127:cursor B] fb: [NOFB], visible: no
<7> [215.654767] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling always-on
<7> [215.654842] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC_off
<7> [215.655510] i915 0000:00:02.0: [drm:gen9_set_dc_state.part.15 [i915]] Setting DC state from 02 to 00
<7> [215.655618] i915 0000:00:02.0: [drm:icl_verify_procmon_ref_values [i915]] Combo PHY A Voltage/Process Info : 0.85V dot0 (low-voltage)
<7> [215.655714] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY A already enabled, won't reprogram it.
<7> [215.655805] i915 0000:00:02.0: [drm:icl_verify_procmon_ref_values [i915]] Combo PHY B Voltage/Process Info : 0.85V dot0 (low-voltage)
<7> [215.655894] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY B already enabled, won't reprogram it.
<7> [215.655994] i915 0000:00:02.0: [drm:icl_verify_procmon_ref_values [i915]] Combo PHY C Voltage/Process Info : 0.85V dot0 (low-voltage)
<7> [215.656086] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY C already enabled, won't reprogram it.
<7> [215.656173] i915 0000:00:02.0: [drm:icl_verify_procmon_ref_values [i915]] Combo PHY D Voltage/Process Info : 0.85V dot0 (low-voltage)
<7> [215.656260] i915 0000:00:02.0: [drm:icl_combo_phys_init [i915]] Combo PHY D already enabled, won't reprogram it.
<7> [215.656337] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling PW_3
<7> [215.656437] i915 0000:00:02.0: [drm:intel_cdclk_dump_config [i915]] Changing CDCLK to 192000 kHz, VCO 768000 kHz, ref 24000 kHz, bypass 12000 kHz, voltage level 0
<7> [215.656614] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:184:DDI B/PHY B]
<7> [215.656689] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:194:DDI TC2/PHY D]
<7> [215.656761] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:196:DP-MST A]
<7> [215.656832] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:197:DP-MST B]
<7> [215.656899] i915 0000:00:02.0: [drm:intel_modeset_verify_disabled [i915]] [ENCODER:198:DP-MST C]
<7> [215.656981] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<7> [215.657060] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 1
<7> [215.657136] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 4
<7> [215.657212] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [215.657316] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 0x2, on? 0) for [CRTC:131:pipe B]
<7> [215.657389] i915 0000:00:02.0: [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7> [215.657510] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DDI_IO_B
<7> [215.657659] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe B
<7> [215.658284] i915 0000:00:02.0: [drm:intel_audio_codec_enable [i915]] [CONNECTOR:185:HDMI-A-1][ENCODER:184:DDI B/PHY B] Enable audio codec on pipe B, 32 bytes ELD
<7> [215.658380] i915 0000:00:02.0: [drm:audio_config_hdmi_pixel_clock [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
<7> [215.658453] i915 0000:00:02.0: [drm:hsw_audio_config_update [i915]] using automatic N
<7> [215.675051] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [215.675256] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:185:HDMI-A-1]
<7> [215.675348] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:131:pipe B]
<7> [215.675556] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.36 [i915]] DPLL 0
<6> [215.717113] PM: suspend entry (deep)
<6> [215.717968] Filesystems sync: 0.000 seconds