Few Suspend tests - incomplete - PM: suspend entry (s2idle)
<7> [194.341682] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [ENCODER:307:DDI A/PHY A][DPRX] 8b/10b, lanes: 2, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [194.342058] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:307:DDI A/PHY A][DPRX] Using DP training pattern TPS1
<7> [194.343618] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:307:DDI A/PHY A][DPRX] Clock recovery OK
<7> [194.343861] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [ENCODER:307:DDI A/PHY A][DPRX] Using DP training pattern TPS2
<7> [194.345858] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [ENCODER:307:DDI A/PHY A][DPRX] Channel EQ done. DP Training successful
<7> [194.346081] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:308:eDP-1][ENCODER:307:DDI A/PHY A][DPRX] Link Training passed at link rate = 270000, lane count = 2
<7> [194.346961] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe A
<7> [194.347409] i915 0000:00:02.0: [drm:intel_edp_backlight_on [i915]]
<7> [194.347665] i915 0000:00:02.0: [drm:intel_backlight_enable [i915]] pipe A
<7> [194.347955] i915 0000:00:02.0: [drm:intel_backlight_set_pwm_level [i915]] set backlight PWM = 96000
<7> [194.358573] i915 0000:00:02.0: [drm:gen9_dbuf_slices_update [i915]] Updating dbuf slices to 0x3
<7> [194.358738] i915 0000:00:02.0: [drm:intel_psr_post_plane_update [i915]] Enabling PSR1
<7> [194.359563] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:308:eDP-1]
<7> [194.359712] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:98:pipe A]
<7> [194.359970] i915 0000:00:02.0: [drm:intel_ddi_get_config [i915]] [ENCODER:307:DDI A/PHY A] Fec status: 0
<7> [194.360118] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
<6> [194.415946] PM: suspend entry (s2idle)
<6> [194.419446] Filesystems sync: 0.003 seconds
Edited by Ravi V