GLK : igt@.* - dmesg-warn - *ERROR* Video mode command 0x00000041 send failed.
<6> [34.254012] [IGT] kms_plane: starting subtest plane-panning-bottom-right-suspend-pipe-B-planes
<7> [34.254825] [drm:drm_mode_addfb2] [FB:167]
<7> [34.342831] [drm:drm_mode_setcrtc] [CRTC:67:pipe A]
<7> [34.343042] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 1920, found 0)
<7> [34.343283] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 2160, found 0)
<7> [34.343546] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 1920, found 0)
<7> [34.343753] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 2160, found 0)
<7> [34.343931] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 2000, found 0)
<7> [34.344108] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 2080, found 0)
<7> [34.344285] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 1200, found 0)
<7> [34.344485] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 1212, found 0)
<7> [34.344663] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 1200, found 0)
<7> [34.344840] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 1212, found 0)
<7> [34.345016] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 1204, found 0)
<7> [34.345193] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 1208, found 0)
<7> [34.345427] i915 0000:00:02.0: [drm:pipe_config_mismatch [i915]] [CRTC:67:pipe A] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 157100, found 0)
<7> [34.345697] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 988) -> ( 0 - 0), size 988 -> 0
<7> [34.345849] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:63:cursor A] ddb ( 988 - 1020) -> ( 0 - 0), size 32 -> 0
<7> [34.346000] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7,*twm, swm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm, swm
<7> [34.346149] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 1, 1, 2, 2, 2, 2, 2, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [34.346299] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 11, 11, 12, 33, 33, 33, 33, 33, 25, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [34.346469] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 12, 12, 13, 34, 34, 34, 34, 34, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
<7> [34.346684] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change
<7> [34.346862] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
<7> [34.347038] i915 0000:00:02.0: [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 4, actual 4
<7> [34.347219] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:67:pipe A] enable: no [modeset]
<7> [34.347440] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [NOFB], visible: no
<7> [34.347618] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no
<7> [34.347793] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 3A] fb: [NOFB], visible: no
<7> [34.347970] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:55:plane 4A] fb: [NOFB], visible: no
<7> [34.348147] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:63:cursor A] fb: [NOFB], visible: no
<7> [34.348511] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling DC off
<7> [34.348815] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
<7> [34.359241] i915 0000:00:02.0: [drm:intel_dsi_disable [i915]]
<7> [34.359670] i915 0000:00:02.0: [drm:intel_dsi_vbt_exec_sequence [i915]] Starting MIPI sequence 7 - MIPI_SEQ_BACKLIGHT_OFF
<7> [34.359851] i915 0000:00:02.0: [drm:mipi_exec_gpio [i915]]
<7> [34.360043] i915 0000:00:02.0: [drm:mipi_exec_delay [i915]]
<7> [34.361279] i915 0000:00:02.0: [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
<3> [34.463477] i915 0000:00:02.0: [drm] *ERROR* Video mode command 0x00000041 send failed.
<7> [34.475428] i915 0000:00:02.0: [drm:intel_dsi_post_disable [i915]]
<7> [34.481471] i915 0000:00:02.0: [drm:bxt_dsi_pll_disable [i915]]
<7> [34.481679] i915 0000:00:02.0: [drm:intel_dsi_vbt_exec_sequence [i915]] Starting MIPI sequence 11 - MIPI_SEQ_POWER_OFF
<7> [34.481860] i915 0000:00:02.0: [drm:mipi_exec_gpio [i915]]
<7> [34.482050] i915 0000:00:02.0: [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
<7> [34.482261] [drm:intel_dump_cdclk_config [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage level 4
<7> [34.482601] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:142:DDI B/PHY B]
<7> [34.482779] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:152:DDI C/PHY C]
<7> [34.482956] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:154:DP-MST A]
<7> [34.483132] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:155:DP-MST B]
<7> [34.483308] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:156:DP-MST C]
<7> [34.483543] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [ENCODER:160:DSI A]
<7> [34.483721] i915 0000:00:02.0: [drm:intel_dsi_get_hw_state [i915]]
<7> [34.483920] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:161:DSI-1]
<7> [34.484102] i915 0000:00:02.0: [drm:intel_dsi_get_hw_state [i915]]
<7> [34.484289] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.131 [i915]] PORT PLL A
<7> [34.484501] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.131 [i915]] PORT PLL B
<7> [34.484688] i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.131 [i915]] PORT PLL C
<7> [34.484955] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:67:pipe A]
<7> [34.485256] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling DC off
<7> [34.485476] i915 0000:00:02.0: [drm:gen9_enable_dc5 [i915]] Enabling DC5
<7> [34.485656] i915 0000:00:02.0: [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
<7> [34.486874] i915 0000:00:02.0: [drm:intel_power_well_disable [i915]] disabling always-onEdited by Tejasree Illipilli