DG1 (8086:4095) HEVC/VP9 video playback hangs (fix is already included)

DG1 HEVC/VP9 decoding in the upstream i915 is always broken, and testing with media-driver and ffmpeg/vaapi will cause the driver to hang immediately.

I recently had the same problem as in i915 after 6.11+ kernel turning on power gating in Xe KMD. After searching, it was caused by DG1 not supporting sub-pipe PG. There is an archived patch in the mailing list that has not been merged. Applying it fixed the problem in i915 and Xe KMD.

https://patchwork.kernel.org/project/intel-gfx/patch/20220721075909.97371-1-rodrigo.vivi@intel.com/

I would be very grateful if someone could help me submit and merge these patches into upstream i915 and xe drivers.

uname -a
Linux 6.13.0-rc3-1-drm-tip-git-g4d485df56628 #25 SMP PREEMPT_DYNAMIC Thu, 19 Dec 2024 12:16:47 +0000 x86_64 GNU/Linux

lspci -vnn
03:00.0 VGA compatible controller [0300]: Intel Corporation DG1 [Iris Xe MAX Graphics] [8086:4905] (rev 01) (prog-if 00 [VGA controller])
        Flags: bus master, fast devsel, latency 0, IRQ 144
        Memory at 50000000 (64-bit, non-prefetchable) [size=16M]
        Memory at 6000000000 (64-bit, prefetchable) [size=4G]
        Expansion ROM at 51000000 [disabled] [size=2M]
        Capabilities: <access denied>
        Kernel driver in use: i915
        Kernel modules: i915, xe

dmesg | grep i915
[    1.270700] i915 0000:03:00.0: Force probing unsupported Device ID 4905, tainting kernel
[    1.270742] i915 0000:03:00.0: [drm] Found dg1 (device ID 4905) discrete display version 12.00 stepping B0
[    1.344611] i915 0000:03:00.0: vgaarb: deactivate vga console
[    1.370565] i915 0000:03:00.0: [drm] Finished loading DMC firmware i915/dg1_dmc_ver2_02.bin (v2.2)
[    1.399276] i915 0000:03:00.0: [drm] GT0: GuC firmware i915/dg1_guc_70.bin version 70.36.0
[    1.399279] i915 0000:03:00.0: [drm] GT0: HuC firmware i915/dg1_huc.bin version 7.9.3
[    1.403806] i915 0000:03:00.0: [drm] GT0: HuC: authenticated for all workloads
[    1.404534] i915 0000:03:00.0: [drm] GT0: GUC: submission enabled
[    1.404534] i915 0000:03:00.0: [drm] GT0: GUC: SLPC enabled
[    1.404768] i915 0000:03:00.0: [drm] GT0: GUC: RC enabled
[    1.504262] i915 0000:03:00.0: [drm] fb0: i915drmfb frame buffer device

HEVC/VP9 decoding hangs:

[   31.088904] i915 0000:03:00.0: [drm] GPU HANG: ecode 12:4:28fffffd
[  389.057962] i915 0000:03:00.0: [drm] GPU HANG: ecode 12:4:28fffffd
[  436.203919] i915 0000:03:00.0: [drm] GPU HANG: ecode 12:4:28fffffd
[ 1420.091142] i915 0000:03:00.0: [drm] GPU HANG: ecode 12:4:28fffffd

Patch for i915 KMD:

From 512428908f34ff0edd5bce7c614092a96017fbc6 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Thu, 21 Jul 2022 03:59:09 -0400
Subject: [PATCH] drm/i915/dg1: Fix power gate sequence.

sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.

HSDES: 1507666497, 1407222020
VLK: 16314, 4304

Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index c864d101faf9..9378d5901c49 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -133,7 +133,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
 			GEN9_MEDIA_PG_ENABLE |
 			GEN11_MEDIA_SAMPLER_PG_ENABLE;
 
-	if (GRAPHICS_VER(gt->i915) >= 12) {
+	if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
 		for (i = 0; i < I915_MAX_VCS; i++)
 			if (HAS_ENGINE(gt, _VCS(i)))
 				pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
-- 
2.47.1

Patch for Xe KMD:

From 3c1c083a15ffd400dfb7fbe46ffa57f9b64cc19c Mon Sep 17 00:00:00 2001
From: nyanmisaka <nst799610810@gmail.com>
Date: Thu, 19 Dec 2024 19:44:44 +0800
Subject: [PATCH] drm/xe: Disbale Coarse Power Gating for DG1

Based on the i915 patch "drm/i915/dg1: Fix power gate sequence."

Sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.

HSDES: 1507666497, 1407222020
VLK: 16314, 4304

Fixes: 38e8c4184ea0 ("drm/xe: Enable Coarse Power Gating")
Signed-off-by: nyanmisaka <nst799610810@gmail.com>
---
 drivers/gpu/drm/xe/xe_gt_idle.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index fd80afeef56a..c73dfdb69647 100644
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -122,10 +122,15 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
 	if (!xe_gt_is_media_type(gt))
 		gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE;
 
-	for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
-		if ((gt->info.engine_mask & BIT(i)))
-			gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |
-						     VDN_MFXVDENC_POWERGATE_ENABLE(j));
+	/* Sub-pipe PG is not present on DG1. Setting these bits can disable
+	 * other power gates and cause GPU hangs on video playbacks.
+	 */
+	if (xe->info.platform != XE_DG1) {
+		for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
+			if ((gt->info.engine_mask & BIT(i)))
+				gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |
+							     VDN_MFXVDENC_POWERGATE_ENABLE(j));
+		}
 	}
 
 	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
-- 
2.47.1