<7> [420.159172] i915 0000:00:02.0: [drm:drm_dp_read_dpcd_caps [drm_display_helper]] AUX USBC1/DDI TC1/PHY B: DPCD: 14 14 c4 01 01 00 01 40 02 02 06 00 00 00 80
<7> [420.159208] i915 0000:00:02.0: [drm:intel_dp_start_link_train [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] Using LINK_BW_SET value 14
<7> [420.159804] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing levels: 0/0/0/0, pre-emphasis levels: 0/0/0/0
<7> [420.159966] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] Using DP training pattern TPS1
<7> [420.161129] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing request: 1/1/1/1, pre-emphasis request: 0/0/0/0
<7> [420.161230] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing levels: 1/1/1/1, pre-emphasis levels: 0/0/0/0
<7> [420.162500] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing request: 2/2/2/2, pre-emphasis request: 0/0/0/0
<7> [420.162597] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing levels: 2/2/2/2, pre-emphasis levels: 0/0/0/0
<7> [420.163867] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] Clock recovery OK
<7> [420.163962] i915 0000:00:02.0: [drm:intel_dp_program_link_training_pattern [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] Using DP training pattern TPS3
<7> [420.165871] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing request: 2/2/2/2, pre-emphasis request: 1/1/1/1
<7> [420.165985] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing levels: 2/2/2/2, pre-emphasis levels: 1/1/1/1
<7> [420.167916] i915 0000:00:02.0: [drm:intel_dp_get_adjust_train [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing request: 2/2/2/2, pre-emphasis request: 0/0/0/0
<7> [420.168029] i915 0000:00:02.0: [drm:intel_dp_set_signal_levels [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] 8b/10b, lanes: 4, vswing levels: 2/2/2/2, pre-emphasis levels: 0/0/0/0
<7> [420.169975] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] Channel EQ done. DP Training successful
<7> [420.170089] i915 0000:00:02.0: [drm:intel_dp_link_train_phy [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B][DPRX] Link Training passed at link rate = 540000, lane count = 4
<7> [420.170632] i915 0000:00:02.0: [drm:intel_enable_transcoder [i915]] enabling pipe B
<7> [420.187552] i915 0000:00:02.0: [drm:intel_audio_codec_enable [i915]] [CONNECTOR:241:DP-1][ENCODER:240:DDI TC1/PHY B] Enable audio codec on [CRTC:134:pipe B], 32 bytes ELD
<7> [420.204278] i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:241:DP-1]
<7> [420.204470] i915 0000:00:02.0: [drm:intel_modeset_verify_crtc [i915]] [CRTC:134:pipe B]
<6> [420.309238] PM: suspend entry (deep)